Abstract: A double-tilt in-situ mechanical sample holder for TEM based on piezoelectric ceramic drive belongs to the field of material microstructure-mechanical properties in-situ characterization, and it comprise two parts of sample holder shaft body and piezoelectric ceramic drive system. The sample holder shaft body comprise tilt stage, sample holder, linear stepping motor, drive rod, drive linkage. The piezoelectric ceramic drive system comprise piezoelectric ceramic loading stage, piezoelectric ceramic, connecting base and the sample loading stage realizing stretch or compression function. The double-axis tilt of the samples in X and Y axis directions is realized by the reciprocating motion back and forth of the drive rod driven by the linear stepping motor. The stretch or compression of the samples is realized by applying voltage on the piezoelectric ceramic to generate displacement and push the sample loading stage by the connecting base.

Abstract: A double-tilt sample holder for TEM, comprising: it comprise the main body of sample holder body, front-end tilt stage, drive rod, linkage, tilt axis, rotation axis, fixed axis of drive rod and sample loading stage. The axis hole is arranged at the front-end tilt stage, which is connected to the main body of the sample holder body by the tilt axis. The linkage, the boss slot and the drive rod slot are connected by the rotation axis. Two through movement guide grooves are designed symmetrically at both sides of the front-end of sample holder body, and the drive rod is fixed by the fixed axis of the drive rod, which restricts the drive rod to move reciprocally in a straight line driven by the linear stepping motor at the back-end of the main body of the holder body, further leading the tilt stage to rotate around the tilt axis. The tilt angle of the sample loading stage can be precisely controlled by the high precision linear stepping motor in the apparatus.

Abstract: The present invention provides a method and a system for ordering browsing histories, wherein the method for ordering browsing histories includes: receiving a triggering instruction of a user for viewing browsing histories; acquiring the geographical location information of a current location; extracting browsing histories corresponding to the geographical location information; and displaying the browsing histories extracted. The present invention also discloses a system for ordering browsing histories. The method and the system for ordering browsing histories provided by the present invention can order the browsing histories according to the geographical location information of the user, and enable the user to quickly find the history to be browsed, thus improving the user experience.

Abstract: A method for preparing a comb-like polyurethane, including: 1) adding a diol to a reaction vessel, stirring, heating, vacuum dehydrating, and cooling the diol; adding a diisocyanate to the diol, and pre-polymerizing the diisocyanate and the diol under vacuum to yield a polyurethane prepolymer; 2) dissolving lysine in a mixture of water and an organic solvent to yield a first solution, adding the first solution to the polyurethane prepolymer to yield a first reaction mixture; stopping stirring and allowing the first reaction mixture to stand for between 10 and 12 hrs, pouring the first reaction mixture into water, and drying a precipitate to yield a polyurethane elastomer containing carboxyl groups; 3) dissolving the polyurethane elastomer in an organic solvent to yield a second solution; adding an epoxy-terminated polyethylene glycol to the second solution, and stirring a resulting mixture at between 110 and 130° C.

Abstract: A flexible circuit board and a cutting device are provided. The flexible circuit board includes a board body including a cutting region. A plurality rows of testing terminals are located in the cutting region, a first spacing being provided between two adjacent rows of testing terminals. The testing terminals can be respectively cut off from the board body along a cutting direction which is along the extending direction of the first spacing in the board body. A testing circuit is located on a surface of the board body. The testing circuit is arranged in a region outside the cutting region and the testing circuit is independently and electrically connected to each row of the testing terminals.

Abstract: A first pair of resistors formed in a first layer of material, and a second pair of resistors formed in the first layer or in a second layer can be wired into a Wheatstone bridge to form a temperature sensor. Either layer can include a semiconductor or a dielectric. In a semiconductor layer, a pair of resistors can be doped areas of the layer, while in a dielectric, a pair of resistors can be material deposited in cavities in the layer, such as material from an added “middle-of-line” (MOL) metallization layer.

Abstract: The present invention relates to the technical field of testing display module, and discloses a display module detection device. The display module detection device comprises a storage module, in which configuration parameters of multiple types of display modules are pre-stored for determining a configuration parameter to be outputted by the storage module based on a type of a display module to be detected, and a test system module being communicatively connected with the storage module and configured for determining an output parameter of a test signal output interface based on the configuration parameter outputted by the storage module.

Abstract: The present invention discloses a touch panel scribing detection device and a detection method thereof. The touch panel scribing detection device includes a loading platform, a scribing standardization unit, a test unit and a signal unit. The touch panel scribing detection device can provide an accurate scribing test path, so the accuracy and efficiency of manual test on a touch panel can be improved.

Abstract: An electromagnetic parameterized cell (EM Pcell) is generated for a local environment of an integrated circuit (IC) design for an electronic design flow. A set of parasitics extracted netlists is developed from a set of Pcell layouts and an external EM environment. The parasitics extracted netlists are simulated to provide a set of performance metrics. When a symbolic view of the EM Pcell is displayed to a designer during a subsequent schematic phase of the design flow, the performance metrics are accessed from a design library, to increase accuracy of parameter value selection for the EM Pcell without a parasitics extraction of the physical layout and generation of a parasitics extracted netlist.

Abstract: A method for preparing a comb-like polyurethane, including: 1) adding a diol to a reaction vessel, stirring, heating, vacuum dehydrating, and cooling the diol; adding a diisocyanate to the diol, and pre-polymerizing the diisocyanate and the diol under vacuum to yield a polyurethane prepolymer; 2) dissolving lysine in a mixture of water and an organic solvent to yield a first solution, adding the first solution to the polyurethane prepolymer to yield a first reaction mixture; stopping stirring and allowing the first reaction mixture to stand for between 10 and 12 hrs, pouring the first reaction mixture into water, and drying a precipitate to yield a polyurethane elastomer containing carboxyl groups; 3) dissolving the polyurethane elastomer in an organic solvent to yield a second solution; adding an epoxy-terminated polyethylene glycol to the second solution, and stirring a resulting mixture at between 110 and 130° C.

Abstract: In an example for implementing a process under a superuser privilege within a computing device, a monitor function library for monitoring an executable function is loaded when the process acquires the superuser privilege. When it is detected that the process runs the executable function, the monitor function library may suspend the running of the executable function, and output process monitoring information. If a feedback to the process monitoring information indicates that it is allowable to perform the executable function, a system function library is invoked to perform the executable function the process runs.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.

Abstract: Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap.

Abstract: A first pair of resistors formed in a first layer of material, and a second pair of resistors formed in the first layer or in a second layer can be wired into a Wheatstone bridge to form a temperature sensor. Either layer can include a semiconductor or a dielectric. In a semiconductor layer, a pair of resistors can be doped areas of the layer, while in a dielectric, a pair of resistors can be material deposited in cavities in the layer, such as material from an added “middle-of-line” (MOL) metallization layer.

Abstract: Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure.

Abstract: A double tilt sample holder for in-situ measuring mechanical and electrical properties of microstructures in transmission electron microscope (TEM) is provided. The sample holder includes a home-made hollow sample holder body, a sensor for measuring mechanical/electrical properties, a pressing piece, a sample holder head, a sensor carrier. The sensor for measuring mechanical/electrical properties is fixed on the sensor carrier on the sample holder head by the pressing piece, while the sensor carrier is connected to the sample holder head through a pair of supporting shafts located on sides of the sample holder head. The sensor carrier can tilt within the plane perpendicular to the ample holder head by revolving around the supporting shafts (i.e. tilting along Y axis at an angle of ±30°). The sample holder also allows obtaining mechanical/electrical parameters concurrently.

Abstract: A double tilt sample holder for in-situ measuring mechanical and electrical properties of microstructures in transmission electron microscope (TEM) is provided. The sample holder includes a home-made hollow sample holder body, a sensor for measuring mechanical/electrical properties, a pressing piece, a sample holder head, a sensor carrier. The sensor for measuring mechanical/electrical properties is fixed on the sensor carrier on the sample holder head by the pressing piece, while the sensor carrier is connected to the sample holder head through a pair of supporting shafts located on sides of the sample holder head. The sensor carrier can tilt within the plane perpendicular to the ample holder head by revolving around the supporting shafts (i.e. tilting along Y axis at an angle of ±30°). The sample holder also allows obtaining mechanical/electrical parameters concurrently.