Abstract: A static CMOS component is operated in a power-down state at the lowest possible voltage that maintains register and internal state levels of the component. A method of operating the static CMOS component includes the steps of selectively supplying a reference voltage at two voltage levels including an operating voltage level and a low reference voltage level, detecting an idle state of the static CMOS component and controlling the selectively supplying step to supply the low reference voltage in response to detection of the idle state. The low reference voltage level is substantially lower than the operating voltage level but is sufficient in voltage amplitude to maintain register and internal state levels of the static CMOS component. An electronic system which performs this method includes a programmable power supply source which selectively supplies an operating voltage and a low voltage which is substantially lower than the operating voltage.

Abstract: A multi-mode home terminal system utilizes a single embedded processor and a single RAM for performing modem operations, graphics/video processing and general purpose control tasks. The multi-mode home terminal system supports a wide range of video/graphics standards, modems and voice algorithms. Home terminal input data to be displayed on an associated monitor can be decoded to any display list format or directly to the system's frame buffer. The display lists, frame buffer, font area, and embedded processor memory are located in the same single random access memory, thus allowing the use of a single RAM for DSP data, display lists, video buffers, voice compression/decompression algorithms and embedded controller tasks. The system is flexible for programming the desired video standard, modem type and display list format. Since both the video function and the embedded processor are supported by the same RAM, a RAM arbiter resolves bus contention.

Abstract: The present invention provides a phase-locked loop in which an internal oscillator is fed into a high resolution tapped delay line. One output of the tapped delay line is selected by selection logic to generate the output clock. The output clock is phase compared with the input signal, which is either a clock signal or a NRZ data signal, and in any case, is a signal with frequency that is a division by two of the frequency of the internal oscillator and the source of which is also the internal oscillator. Then a decision is made, according to the phase detection, whether to select the next output of the delay line, the previous one, or remain with the current one. Therefore, if a change in the frequency is needed, then if an integer multiple or division of the original frequency is selected for the internal oscillator, synchronization will be unchanged, and furthermore, both the output clock and the input signal will simultaneously switch to the new frequency.

Abstract: A method and apparatus for observing the contents on internal memory-mapped registers of controllers and co-processors which have been integrated on-chip with a central processing unit ("CPU"). The CPU asserts a first signal when access to internal memory is requested and deactivates a second signal which would normally allow simultaneous access to both internal and external memory locations. In this way, the contents of internal memory may be observed in real time.