Patents by Inventor Ze'ev Wurman
Ze'ev Wurman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9577642Abstract: A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated circuit, where at least one of the devices has at least one unused designated dice line and at least one of the devices is a configurable device; and interconnecting at least two of the devices using Through Silicon Vias.Type: GrantFiled: November 7, 2010Date of Patent: February 21, 2017Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Ze'ev Wurman
-
Patent number: 9219005Abstract: A 3D IC based mobile system including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a plurality of thermal paths between the second mono-crystallized transistors and a heat removal apparatus, where at least one of the plurality of thermal paths includes a thermal contact adapted to conduct heat and not conduct electricity; and a heat spreader layer between the second layer and the at least one metal layer.Type: GrantFiled: September 20, 2012Date of Patent: December 22, 2015Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist, Ze'ev Wurman
-
Patent number: 9136153Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and includes aluminum or copper; a second layer including second transistors; where the second transistors are aligned to the first transistors with a less than 40 nm alignment error, and where the second layer is overlying the first interconnection layer, and where at least one of the second transistors has a back-bias structure designed to modify the performance of at least one of the second transistors.Type: GrantFiled: June 8, 2012Date of Patent: September 15, 2015Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
-
Patent number: 9029173Abstract: A method for formation of a semiconductor device, the method including: providing a first mono-crystalline layer including first transistors and first alignment marks; providing an interconnection layer including aluminum or copper on top of the first mono-crystalline layer; and then forming a second mono-crystalline layer on top of the first mono-crystalline layer interconnection layer by using a layer transfer step, and then processing second transistors on the second mono-crystalline layer including a step of forming a gate dielectric, where at least one of the second transistors is a p-type transistor and at least one of the second transistors is an n-type transistor.Type: GrantFiled: October 18, 2011Date of Patent: May 12, 2015Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Ze'ev Wurman
-
Publication number: 20140059411Abstract: A computing system including a processor, display, pointing device and memory; wherein the memory includes a text file, a graphics file corresponding to said text file and executable instructions to perform at least these actions (i) identify a selection of an alphanumeric identifier within a displayed text file, and then (ii) identify the appearance of the identifier in a corresponding graphics file, and then (iii) display a page of the graphics file comprising the appearance of the identifier.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Ze'ev Wurman, Brian Cronquist
-
Patent number: 8642416Abstract: A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.Type: GrantFiled: June 28, 2011Date of Patent: February 4, 2014Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist, Ze'ev Wurman
-
Patent number: 8492886Abstract: An integrated circuit including a first layer of logic circuits, and a second layer of logic circuits overlaying the first layer, wherein the first layer includes a multiplicity of flip-flops wherein each of the flip-flops has at least one connection to the second layer, and wherein the second layer includes at least one logic circuit with inputs including the connection and with at least one output connected to the first layer.Type: GrantFiled: November 22, 2010Date of Patent: July 23, 2013Assignee: Monolithic 3D IncInventors: Zvi Or-Bach, Ze'ev Wurman
-
Publication number: 20130122672Abstract: A method for formation of a semiconductor device including a first wafer including a first single crystal layer comprising first transistors and first alignment mark, the method including: implanting to form a doped layer within a second wafer; forming a second mono-crystalline layer on top of the first wafer by transferring at least a portion of the doped layer using layer transfer step, and completing the formation of second transistors on the second mono-crystalline layer including a step of forming a gate dielectric followed by second transistors gate formation step, wherein the second transistors are horizontally oriented.Type: ApplicationFiled: June 28, 2011Publication date: May 16, 2013Applicant: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist, Ze'ev Wurman
-
Publication number: 20130095580Abstract: A method for formation of a semiconductor device including a first mono-crystalline layer comprising first transistors and first alignment marks, the method comprising forming a doped layer within a wafer, forming a second mono-crystalline layer on top of the first mono-crystalline layer by transferring at least a portion of the doped layer using layer transfer step, and processing second transistors on the second mono-crystalline layer comprising a step of forming a gate dielectric, wherein the second transistors are horizontally oriented.Type: ApplicationFiled: October 18, 2011Publication date: April 18, 2013Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Ze'ev Wurman
-
Patent number: 8378715Abstract: A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die.Type: GrantFiled: August 24, 2012Date of Patent: February 19, 2013Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Ze'ev Wurman
-
Patent number: 8362800Abstract: A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer.Type: GrantFiled: October 13, 2010Date of Patent: January 29, 2013Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Ze'ev Wurman
-
Publication number: 20130020707Abstract: A 3D IC based system including: a first semiconductor layer including first alignment marks and first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer; and wherein the second transistors include a plurality of N-type transistors and P-type transistors, and wherein the second mono-crystallized semiconductor layer is transferred from a reusable donor wafer.Type: ApplicationFiled: September 20, 2012Publication date: January 24, 2013Applicant: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak Sekar, Brian Cronquist, Ze'ev Wurman
-
Publication number: 20120322203Abstract: A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die.Type: ApplicationFiled: August 24, 2012Publication date: December 20, 2012Applicant: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Ze'ev Wurman
-
Publication number: 20120248595Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.Type: ApplicationFiled: June 8, 2012Publication date: October 4, 2012Applicant: MonolithlC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
-
Patent number: 8273610Abstract: A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.Type: GrantFiled: October 14, 2011Date of Patent: September 25, 2012Assignee: MonolithIC 3D Inc.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Ze'ev Wurman, Paul Lim
-
Patent number: 8258810Abstract: A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer.Type: GrantFiled: September 30, 2010Date of Patent: September 4, 2012Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Ze'ev Wurman
-
Publication number: 20120194218Abstract: A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer.Type: ApplicationFiled: September 30, 2010Publication date: August 2, 2012Inventors: Zvi Or-Bach, Ze'ev Wurman
-
Publication number: 20120194216Abstract: A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer.Type: ApplicationFiled: October 13, 2010Publication date: August 2, 2012Inventors: Zvi Or-Bach, Ze'ev Wurman
-
Publication number: 20120196390Abstract: A method for manufacturing system includes 3D-IC comprising at least first layer of first transistors and second layers of second transistors and, perform a test for the circuit constructed with said first transistors and switch in function constructed with said second transistors to replace function constructed with said first transistors.Type: ApplicationFiled: November 22, 2010Publication date: August 2, 2012Inventors: Zvi Or-Bach, Ze'ev Wurman
-
Publication number: 20120193806Abstract: A three dimensional semiconductor device includes a first die; and a second die overlaying the first die, wherein said first die comprises signals are selectively coupleable to the second die using Through Silicon Vias.Type: ApplicationFiled: November 7, 2010Publication date: August 2, 2012Inventors: Zvi Or-Bach, Ze'ev Wurman