Abstract: The present invention relates to the area of lifestyle devices and applications, particularly to daily trackers of activities, such as pedometers used for exercise monitoring, and working in collaboration with tools analyzing and planning the food intake and amount of exercises to keep or obtain the desired weight. This invention aims at better controlling: fitness level, food consumption, blood glucose level and weight of a person throughout the day. For daily and weekly tracking of the weight, the ingested and expended calories are reported. Calories meal goals are adjusting daily reflecting the over the goal exercise levels as well as mismatch in food consumed and meal goals. The method for better blood glucose control predicts the effects of the food ingested on raising a post-meal blood glucose level, and suggests a suitable timing and the duration of the exercise following the food intake to minimize a post-meal blood glucose peak.

Abstract: The present invention related to the area of lifestyle devices, particularly to pedometers used for exercise tracking. This invention aims at accurate recording of steps, speeds, distances, type of motion (walk and run) and calories expenditure, independently of the personal characteristics (age, gender, weight and height). The invention uses sub-band decomposition filters that produce non-distorted sine wave regardless of personal traits and the type of walking or running. Low-complexity zero-crossing step detection is subsequently applied, and the step length and energy expenditure information is then extracted. The method for goals tracking is included for independent types of goals: steps, energy, distance and duration.

Abstract: The present invention relates to an automata unit, a tool for designing circuitry and/or checker circuitry, and a method for manufacturing hardware circuitry. The automata unit includes an input unit for receiving assertions using Boolean expressions, an automata generator for translating the assertions into automata, and an automata adaptor. The automata generator uses a dual layer symbolic alphabet for representing the assertions, and the automata adaptor adapts automata algorithms so as to support the symbolic alphabet in the generated automata. The tools for designing circuitry and checker circuitry rely on the automata unit, and further include an assertion unit and either a circuit generator or a checker generator.

Abstract: The present invention relates to an automata unit, a tool for designing circuitry and/or checker circuitry, and a method for manufacturing hardware circuitry. The automata unit includes an input unit for receiving assertions using Boolean expressions, an automata generator for translating the assertions into automata, and an automata adaptor. The automata generator uses a dual layer symbolic alphabet for representing the assertions, and the automata adaptor adapts automata algorithms so as to support the symbolic alphabet in the generated automata. The tools for designing circuitry and checker circuitry rely on the automata unit, and further include an assertion unit and either a circuit generator or a checker generator.

Abstract: The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.

Abstract: A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.