Abstract: This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.

Abstract: This application relates to a data transmission circuit, a method making it, and a storage device. The circuit includes a mode register data storage unit and an array area data storage unit. The mode register data storage unit outputs mode register data in response to a first clock signal; the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the array area data storage unit receives array area data in response to the first pointer signal, and outputs the array area data in response to the second pointer signal. This technic can accurately control the mode register data and the array area data to output through the respective output channels in turn.

Abstract: A method for checking a data processing circuit includes the following. Performance check files of a plurality of timing sequence logic elements in the data processing circuit are acquired, and the data processing circuit is simulated based on the performance check files of the plurality of timing sequence logic elements, so as to obtain timing sequence information of the respective timing sequence logic elements.

Abstract: A method for determining performance of sequential logic elements includes the following operations. To check a circuit, a performance check file corresponding to each of the sequential logic elements of the circuit is obtained; and the circuit is separately simulated to obtain the simulation result, by using a plurality of simulation waveforms, based on the performance check file corresponding to each of the sequential logic elements. The performance check file may be used to determine, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result.

Abstract: The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

Abstract: A method for evaluating performance of a sequential logic element includes: inputting a preset clock signal and a data signal to a sequential logic element to be tested; decrementing a setup time of the sequential logic element from a first preset value to a second preset value based on a preset decrement step, where the first preset value is determined by a setup time when the sequential logic element to be tested outputs a target sampled value, and the second preset value is determined by a setup time when the sequential logic element outputs a reverse value of the target sampled value; and determining an evaluation parameter of the sequential logic element based on a sampled value output by the sequential logic element after each decrement of the setup time, and evaluating performance of the sequential logic element based on the evaluation parameter of the sequential logic element to be tested.

Abstract: Embodiments relate to a clock counter, a method for clock counting, and a storage apparatus. The clock counter includes a clock frequency-dividing circuit, a plurality of counting circuits, and an adding circuit. The clock frequency-dividing circuit receives a clock signal and divide a frequency of the clock signal to output a plurality of frequency-divided clock signals, sum of number of pulses of the plurality of frequency-divided clock signals being equal to number of pulses of the clock signal. The plurality of counting circuits are connected to the clock frequency-dividing circuit, each of the plurality of counting circuits being configured to respectively count pulses for each of the plurality of frequency-divided clock signals and generate an initial count value. The adding circuit is connected to the plurality of counting circuits, and adds up the initial count values of the plurality of counting circuits to generate a target count value.

Abstract: A circuit for controlling calibration includes a process circuit, an off-chip calibration circuit and a mode switching circuit. The process circuit is configured to perform, in a first test mode, a process corner test on the memory to obtain a test result signal, the test result signal being used for determining a process corner parameter. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a controller, the first calibration code being determined by the controller according to a current environment parameter of the memory and the process corner parameter.

Abstract: A calibration control circuit includes an off-chip calibration circuit, an on-chip calibration circuit and a mode switching circuit. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a user. The on-chip calibration circuit is configured to receive an enable signal and perform a ZQ self-calibration process on the memory to obtain a second calibration code adapted to a current environmental parameter when the enable signal is in an active state. The mode switching circuit is configured to receive a calibration mode signal, the first calibration code and the second calibration code, and determine the first calibration code as a ZQ calibration code when the calibration mode signal indicates an off-chip calibration mode, or, determine the second calibration code as the ZQ calibration code when the calibration mode signal indicates an on-chip calibration mode.

Abstract: This application relates to a data transmission circuit, a method, and a storage device. The data transmission circuit includes a delay module and a mode register data processing unit. The delay module delays a first preset time when receiving a mode register read command, and generates delayed read command. The mode register data processing unit is connected to the delay module, and reads setting parameters from the mode register in response to the mode register read command, and outputs the setting parameters in response to the delayed read command.

Abstract: A method and an apparatus for determining a delay parameter, a computer readable storage medium, and an electronic device are provided. The method for determining the delay parameter includes: determining (S210) a setup time of a clock signal in a memory relative to a DQ data signal; dividing (S220) the clock signal into a plurality of clock sub-signals, and determining (S220) a target sampling delay of the plurality of clock sub-signals relative to the DQ data signal; and determining (S230), according to the target sampling delay and the setup time, a delay parameter of the DQ data signal relative to the clock signal.

Abstract: The present application relates to a circuit simulation test method and apparatus, a device, and a medium. The method includes: creating a parametric data model, wherein the parametric data model is configured to generate preset write data based on a preset parameter; creating a test platform, wherein the test platform is configured to generate a test result based on the preset write data; creating an eye diagram generation module, wherein the eye diagram generation module is configured to generate a data eye diagram based on the test result; and conducting a simulation test, inputting the preset write data to the test platform and obtaining the test result, and generating the data eye diagram by using the eye diagram generation module.

Abstract: Embodiments provide a method and apparatus for capacitor demand evaluation in a PDN that includes at least one power bus provided with multiple nodes. The multiple nodes are distributed at different positions of the power bus. Each of the multiple nodes is connected to multiple capacitors connected in parallel. Each of the multiple capacitors is provided with a respective one of control switches. The method includes: Multiple adjustment operations are performed. Upon accomplishment of each of the multiple adjustment operations, a respective IR drop of the power bus and a respective running speed of the load circuit are detected; for each of different nodes on the power bus, an ideal capacitance of the node is determined according to the IR drops of the power bus and running speeds of the load circuit detected through the multiple adjustment operations.

Abstract: A circuit simulation method includes the following: a key character string corresponding to at least one target power supply node is determined; a node identifier corresponding to the at least one target power supply node is searched out from a first netlist corresponding to the to-be-simulated circuit according to the key character string; and a power supply voltage file corresponding to the at least one target power supply node is generated according to the searched-out node identifier, and the to-be-simulated circuit is simulated according to the power supply voltage file. The circuit simulation method and the device provided by the embodiments of the present disclosure may rapidly generate the power supply voltage file corresponding to the target power supply node, which can not only effectively improve the circuit simulation efficiency, but also ensure the accuracy of a simulation result.

Abstract: Embodiments relate to a clock counter, a method for clock counting, and a storage apparatus. The clock counter includes a clock frequency-dividing circuit, a plurality of counting circuits, and an adding circuit. The clock frequency-dividing circuit receives a clock signal and divide a frequency of the clock signal to output a plurality of frequency-divided clock signals, sum of number of pulses of the plurality of frequency-divided clock signals being equal to number of pulses of the clock signal. The plurality of counting circuits are connected to the clock frequency-dividing circuit, each of the plurality of counting circuits being configured to respectively count pulses for each of the plurality of frequency-divided clock signals and generate an initial count value. The adding circuit is connected to the plurality of counting circuits, and adds up the initial count values of the plurality of counting circuits to generate a target count value.

Abstract: An interface circuit is configured to receive a data signal according to a data strobe signal. The method for evaluating performance of an interface circuit includes: a reference voltage of the interface circuit is scanned to obtain each reference voltage; a sampling point of the data signal by the data strobe signal to is scanned; a test result of the interface circuit under each reference voltage and each sampling point is obtained; and a data eye diagram is generated according to the test result. The performance of the interface circuit can be detected in combination with the scanning of the reference voltage.

Abstract: The present application discloses a design method, a design device, a computer device, and a storage medium for a chip. Where, the design method of the chip includes creating a power bus network according to position of the pad and the chip layout floor plan, determines the position of the power port of the circuit module in the power bus network, and creates a power supply network model according to the power bus network, according to the power supply network model and the power port of the circuit module generates a network table with a power supply network in the power supply port of the power bus network, and circuit simulation is performed according to a network table in which the power supply network is embedded. The design method, design device, computer device and storage medium provided herein, shorten the chip design development cycle, and reduce design costs.