Patents by Inventor Zenja Chao

Zenja Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • I/O bus to system interface
    Patent number: 5261057
    Abstract: An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurality of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.
    Type: Grant
    Filed: July 7, 1992
    Date of Patent: November 9, 1993
    Assignee: Wang Laboratories, Inc.
    Inventors: Richard W. Coyle, Zenja Chao, Thomas B. Berg
  • Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
    Patent number: 5003463
    Abstract: An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurallity of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.
    Type: Grant
    Filed: June 30, 1988
    Date of Patent: March 26, 1991
    Assignee: Wang Laboratories, Inc.
    Inventors: Richard W. Coyle, Zenja Chao, Thomas B. Berg