Abstract: An extended system includes at least one peripheral component interconnect express (PCIE) connector and a control device. The PCIE connector is suitable for connecting to at least one server device. The control device is connected to PCIE connector. According to at least one working voltage generated by the server device, the control device turns on the extended system and ignores a power control signal generated by the extended system, or the control unit generates at least one wakeup signal according to the power control signal generated by the extended system and transmits the wakeup signal to the server device, so that the server device may turn on and generate a working voltage.

Abstract: A power generating apparatus includes a power supply, a first sub-end circuit, a second sub-end circuit and an integrated signal generator. The first and second sub-end circuits respectively generate first and second sub-end standby power. The first sub-end circuit receives a first integrated control signal. The second sub-end circuit receives a second integrated control signal. The first sub-end circuit cuts off the first sub-end standby power according to the first integrated control signal and turns on the first sub-end standby power again after a first delay time. The second sub-end circuit cuts off the second sub-end standby power according to the second integrated control signal, and turns on the second sub-end standby power again after a second delay time. The integrated signal generator generates the first and second integrated control signals.

Abstract: A firmware update device and a firmware update method are provided. The firmware update device includes a first storage medium, a baseboard management controller (BMC), a retimer card, and a processor. The first storage medium stores firmware configuration data. The BMC is coupled to the first storage medium, wherein the BMC is configured to update the firmware configuration data. The retimer card stores a card identifier and firmware. The processor is coupled to the first storage medium and the BMC, wherein the processor detects the card identifier of the retimer card and update the firmware of the retimer card according to the firmware configuration data corresponding to the card identifier in response to identifying the card identifier after the retimer card is coupled to the processor.

Abstract: A firmware update device and a firmware update method are provided. The firmware update device includes a first storage medium, a baseboard management controller (BMC), a retimer card, and a processor. The first storage medium stores firmware configuration data. The BMC is coupled to the first storage medium, wherein the BMC is configured to update the firmware configuration data. The retimer card stores a card identifier and firmware. The processor is coupled to the first storage medium and the BMC, wherein the processor detects the card identifier of the retimer card and update the firmware of the retimer card according to the firmware configuration data corresponding to the card identifier in response to identifying the card identifier after the retimer card is coupled to the processor.

Abstract: A power generating apparatus includes a power supply, a first sub-end circuit, a second sub-end circuit and an integrated signal generator. The first and second sub-end circuits respectively generate first and second sub-end standby power. The first sub-end circuit receives a first integrated control signal. The second sub-end circuit receives a second integrated control signal. The first sub-end circuit cuts off the first sub-end standby power according to the first integrated control signal and turns on the first sub-end standby power again after a first delay time. The second sub-end circuit cuts off the second sub-end standby power according to the second integrated control signal, and turns on the second sub-end standby power again after a second delay time. The integrated signal generator generates the first and second integrated control signals.

Abstract: An extended system includes at least one peripheral component interconnect express (PCIE) connector and a control device. The PCIE connector is suitable for connecting to at least one server device. The control device is connected to PCIE connector. According to at least one working voltage generated by the server device, the control device turns on the extended system and ignores a power control signal generated by the extended system, or the control unit generates at least one wakeup signal according to the power control signal generated by the extended system and transmits the wakeup signal to the server device, so that the server device may turn on and generate a working voltage.

Abstract: A framework for system power control of a dual-port non-volatile memory storage device is provided. The electronic system includes a storage device, two hosts and a control circuit within each of the two hosts. Each host filters signals for shortly turning off a power supply of the storage device during a process of boot and reboot of the host. When one of the hosts enters a turn-off state, it is detected whether another one of the hosts is running, and the one of the hosts does not control the power supply if the another one of the hosts is running. Two control signals of the two hosts control the power supply of the storage device through an AND gate.

Abstract: A framework for system power control of a dual-port non-volatile memory storage device is provided. The electronic system includes a storage device, two hosts and a control circuit within each of the two hosts. Each host filters signals for shortly turning off a power supply of the storage device during a process of boot and reboot of the host. When one of the hosts enters a turn-off state, it is detected whether another one of the hosts is running, and the one of the hosts does not control the power supply if the another one of the hosts is running. Two control signals of the two hosts control the power supply of the storage device through an AND gate.

Abstract: A connecting circuitry is disclosed. The connecting circuitry is coupled to a storage device, a first motherboard and a second motherboard, and controlled by a first control signal and a second control signal to switch over to a first mode, to a second mode and to a third mode. The connecting circuitry includes a first exchanging unit; a second exchanging unit; and a first multiplexing unit, electrical connected to the first exchanging unit and the second exchanging unit; wherein the first mode is the storage device being only accessed by the first motherboard, the second mode is the storage device being only accessed by the second motherboard, and the third mode is the storage device being accessed by both the first motherboard and the second motherboard.

Abstract: A connecting circuitry is disclosed. The connecting circuitry is coupled to a storage device, a first motherboard and a second motherboard, and controlled by a first control signal and a second control signal to switch over to a first mode, to a second mode and to a third mode. The connecting circuitry includes a first exchanging unit; a second exchanging unit; and a first multiplexing unit, electrical connected to the first exchanging unit and the second exchanging unit; wherein the first mode is the storage device being only accessed by the first motherboard, the second mode is the storage device being only accessed by the second motherboard, and the third mode is the storage device being accessed by both the first motherboard and the second motherboard.