Patents by Inventor Zhao Cheng
Zhao Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180272527Abstract: In an approach to creating assembly plan for disaster mitigation, one or more computer processors identify one or more triggering events. The one or more computer processors receive one or more configuration parameters for one or more assembly plans pertaining to the one or more triggering events. The one or more computer processors analyze the one or more configuration parameters to determine necessary configuration parameters based upon the identified one or more triggering events. The one or more computer processors create the one or more assembly plans containing one or more instructions for one or more self-assembling robots based on the determined necessary configuration parameters. The one or more computer processors send the one or more assembly plans to one or more self-assembling robots.Type: ApplicationFiled: March 24, 2017Publication date: September 27, 2018Inventors: Zhao Cheng, Luyao Li, Ramesh V. Raj, Kyle D. Robeson
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Publication number: 20180240790Abstract: A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.Type: ApplicationFiled: April 13, 2018Publication date: August 23, 2018Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
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Patent number: 10035259Abstract: In an approach to creating assembly plan for disaster mitigation, one or more computer processors identify one or more triggering events. The one or more computer processors receive one or more configuration parameters for one or more assembly plans pertaining to the one or more triggering events. The one or more computer processors analyze the one or more configuration parameters to determine necessary configuration parameters based upon the identified one or more triggering events. The one or more computer processors create the one or more assembly plans containing one or more instructions for one or more self-assembling robots based on the determined necessary configuration parameters. The one or more computer processors send the one or more assembly plans to one or more self-assembling robots.Type: GrantFiled: September 15, 2017Date of Patent: July 31, 2018Assignee: International Business Machines CorporationInventors: Zhao Cheng, Luyao Li, Ramesh V. Raj, Kyle D. Robeson
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Patent number: 9947646Abstract: A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.Type: GrantFiled: April 21, 2017Date of Patent: April 17, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
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Publication number: 20170271469Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Yu-Lien Huang, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
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Publication number: 20170229440Abstract: A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.Type: ApplicationFiled: April 21, 2017Publication date: August 10, 2017Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
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Patent number: 9673292Abstract: A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.Type: GrantFiled: November 25, 2015Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
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Publication number: 20170141104Abstract: A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
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Patent number: 9633999Abstract: A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes.Type: GrantFiled: November 16, 2015Date of Patent: April 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
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Publication number: 20160079383Abstract: A semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
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Publication number: 20160043224Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.Type: ApplicationFiled: October 20, 2015Publication date: February 11, 2016Inventors: Yu-Lien Huang, Zhao-Cheng Chen
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Patent number: 9202691Abstract: In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers.Type: GrantFiled: January 18, 2013Date of Patent: December 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, Chi-Wen Liu, Zhao-Cheng Chen, Ming-Huan Tsai, Clement Hsingjen Wann
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Patent number: 9171762Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.Type: GrantFiled: November 1, 2012Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, Zhao-Cheng Chen
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Patent number: 9130059Abstract: A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure. The first dummy gate structure is removed after forming the protective layer, thereby providing a first trench. A capping layer (e.g., silicon) is formed in the first trench. A metal gate structure may be formed on the capping layer. The protective layer may protect the second dummy gate structure during the removal of the first dummy gate structure.Type: GrantFiled: January 18, 2013Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsu-Hsiu Perng, Zhao-Cheng Chen, Chun-Hsiang Fan, Ming-Huan Tsai
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Publication number: 20140206161Abstract: A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure. The first dummy gate structure is removed after forming the protective layer, thereby providing a first trench. A capping layer (e.g., silicon) is formed in the first trench. A metal gate structure may be formed on the capping layer. The protective layer may protect the second dummy gate structure during the removal of the first dummy gate structure.Type: ApplicationFiled: January 18, 2013Publication date: July 24, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsu-Hsiu Perng, Zhao-Cheng Chen, Chun-Hsiang Fan, Ming-Huan Tsai
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Publication number: 20140203333Abstract: In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers. Further, a device having a modified profile metal gate for example having at least one layer of the metal.Type: ApplicationFiled: January 18, 2013Publication date: July 24, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien Huang, Chi-Wen Liu, Zhao-Cheng Chen, Ming-Huan Tsai, Clement Hsingjen Wann
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Patent number: 8756958Abstract: An impulse type shock wave flash dyeing machine is disclosed. A row of joint nozzles can send out high-speed air flows to prompt fibrous fabric to spread out and move in the dyeing machine through the effect of impulse. Dyes or processing agents may be converted into fine mist and is carried by the high-speed air flows to blast the fibrous fabric (3). Therefore, the dyes or processing agents can enter the fibrous fabric (3) quickly and can diffuse or spread out in the fibrous fabric (3) swiftly through strong elastic and inelastic collisions as well as the effect of shock wave. Such collisions and effect can impart enough energy to the dyes or processing agents and convert non-activated molecules into activated molecules. In addition, the effect of corona discharge may be used to generate high-energy particles and hence the goals of clean and swift processes may be achieved.Type: GrantFiled: August 1, 2010Date of Patent: June 24, 2014Inventor: Jiang Zhao-Cheng
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Publication number: 20140117456Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.Type: ApplicationFiled: November 1, 2012Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien Huang, Zhao-Cheng Chen
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Publication number: 20120024017Abstract: An impulse type shock wave flash dyeing machine is disclosed. A row of joint nozzles can send out high-speed air flows to prompt fibrous fabric to spread out and move in the dyeing machine through the effect of impulse. Dyes or processing agents may be converted into fine mist and is carried by the high-speed air flows to blast the fibrous fabric (3). Therefore, the dyes or processing agents can enter the fibrous fabric (3) quickly and can diffuse or spread out in the fibrous fabric (3) swiftly through strong elastic and inelastic collisions as well as the effect of shock wave. Such collisions and effect can impart enough energy to the dyes or processing agents and convert non-activated molecules into activated molecules. In addition, the effect of corona discharge may be used to generate high-energy particles and hence the goals of clean and swift processes may be achieved.Type: ApplicationFiled: August 1, 2010Publication date: February 2, 2012Inventor: Zhao-Cheng JIANG
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Publication number: 20060034696Abstract: The present invention relates to a sector of fan and its manufacturing method, including non-skeleton sector and skeleton sector. The non-skeleton sector of fan is molded by injecting polyurethane foam into a sector molding die; the skeleton sector of fan is comprised of a main body and a framework, wherein said main body and the framework are molded together in similar shape with solid casting resin or other similar material; said framework made of steel wire according the sector's shape and size is comprised of an outer shaped ring, reinforcing ribs and a core bar, if necessary inner shaped rings and crossing reinforcing ribs employed for enhancing the intensity of the sector, but it is always in grid structure. Said outer shaped ring, the reinforcing ribs and the core bar are fastened together, and then an assembling disk is fixed on the back end.Type: ApplicationFiled: August 10, 2004Publication date: February 16, 2006Inventor: Zhao-Cheng Chen