Patents by Inventor Zhaoyin Daniel WU

Zhaoyin Daniel WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11735519
    Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 22, 2023
    Assignee: XILINX, INC.
    Inventors: Zhaoyin Daniel Wu, Parag Upadhyaya, Hong Shi
  • Patent number: 11668874
    Abstract: Disclosed herein is an optical filter configured for wavelength division and multiplexing capable of transmitting and receiving signals. The optical filter includes an optical waveguide configured to receive at an input multiple signals with different wavelengths. The optical filter includes a plurality of channels coupled at different locations along a length of the optical waveguide. Each of the plurality of channels is configured to transmit a respective one of the multiple signals. A number of ring filter stages in a first channel of the plurality of channels that is closer to the input of the optical waveguide is greater than a second channel in the plurality of channels further away from the input of the optical waveguide.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: June 6, 2023
    Assignee: XILINX, INC.
    Inventors: Zhaoyin Daniel Wu, Chuan Xie, Mayank Raj, Parag Upadhyaya
  • Patent number: 11575497
    Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: February 7, 2023
    Assignee: XILINX, INC.
    Inventors: Wenfeng Zhang, Zhaoyin Daniel Wu, Parag Upadhyaya
  • Publication number: 20220415788
    Abstract: A package device comprises a first transceiver comprising a first integrated circuit (IC) die and transmitter circuitry, and a second transceiver comprising a second IC die and receiver circuitry. The receiver circuitry is coupled to the transmitter circuitry via a channel. The package device further comprises an interconnection device connected to the first IC die and the second IC die. The interconnection device comprises a channel connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element disposed external to the first IC die and the second IC die and along the channel.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Zhaoyin Daniel WU, Parag UPADHYAYA, Hong SHI
  • Publication number: 20220407676
    Abstract: In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Wenfeng ZHANG, Zhaoyin Daniel WU, Parag UPADHYAYA