Patents by Inventor Zhefu Wang

Zhefu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741459
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 11, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Patent number: 10199281
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: February 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Publication number: 20190035699
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Application
    Filed: October 2, 2018
    Publication date: January 31, 2019
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Patent number: 10103073
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 16, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Publication number: 20180166347
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Application
    Filed: February 7, 2018
    Publication date: June 14, 2018
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Patent number: 9911664
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Publication number: 20170365532
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Application
    Filed: September 1, 2017
    Publication date: December 21, 2017
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Patent number: 9754846
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 5, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Publication number: 20150371907
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 24, 2015
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Publication number: 20150371913
    Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 24, 2015
    Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
  • Patent number: 7444812
    Abstract: A microelectromechanical systems (MEMS) based heat engine capable of converting thermal energy gradients into mechanical or electrical energy, as well as its fabrication process is disclosed. This heat engine design consists of a stressed oscillating beam formed from a shape memory alloy (SMA) thin film. As the temperature of the beam changes, its shape changes due to the phase transformation of the shape memory alloy, causing it to oscillate between a hot source and a cold source. Due to the hysteretic behavior of the phase transformation, the oscillating SMA cantilever beam produces a net mechanical work output that may be either converted to electrical energy or mechanically linked to other MEMS devices.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: November 4, 2008
    Inventors: Scott Ryan Kirkpatirck, Azad Siahmakoun, Thomas McDaniel Adams, Zhefu Wang
  • Publication number: 20060162331
    Abstract: A microelectromechanical systems (MEMS) based heat engine capable of converting thermal energy gradients into mechanical or electrical energy, as well as its fabrication process is disclosed. This heat engine design consists of a stressed oscillating beam formed from a shape memory alloy (SMA) thin film. As the temperature of the beam changes, its shape changes due to the phase transformation of the shape memory alloy, causing it to oscillate between a hot source and a cold source. Due to the hysteretic behavior of the phase transformation, the oscillating SMA cantilever beam produces a net mechanical work output that may be either converted to electrical energy or mechanically linked to other MEMS devices.
    Type: Application
    Filed: January 27, 2005
    Publication date: July 27, 2006
    Inventors: Scott Kirkpatirck, Azad Siahmakoun, Thomas Adams, Zhefu Wang