Patents by Inventor Zhefu Wang
Zhefu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10741459Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.Type: GrantFiled: October 2, 2018Date of Patent: August 11, 2020Assignee: Applied Materials, Inc.Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
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Patent number: 10199281Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.Type: GrantFiled: February 7, 2018Date of Patent: February 5, 2019Assignee: Applied Materials, Inc.Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
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Publication number: 20190035699Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.Type: ApplicationFiled: October 2, 2018Publication date: January 31, 2019Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
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Patent number: 10103073Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.Type: GrantFiled: September 1, 2017Date of Patent: October 16, 2018Assignee: Applied Materials, Inc.Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
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Publication number: 20180166347Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.Type: ApplicationFiled: February 7, 2018Publication date: June 14, 2018Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
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Patent number: 9911664Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.Type: GrantFiled: June 23, 2014Date of Patent: March 6, 2018Assignee: Applied Materials, Inc.Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
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Publication number: 20170365532Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.Type: ApplicationFiled: September 1, 2017Publication date: December 21, 2017Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
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Patent number: 9754846Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.Type: GrantFiled: June 23, 2014Date of Patent: September 5, 2017Assignee: Applied Materials, Inc.Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
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Publication number: 20150371907Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.Type: ApplicationFiled: June 23, 2014Publication date: December 24, 2015Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
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Publication number: 20150371913Abstract: In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.Type: ApplicationFiled: June 23, 2014Publication date: December 24, 2015Inventors: Wei Lu, Zhefu Wang, Zhihong Wang, Hassan G. Iravani, Dominic J. Benvegnu, Ingemar Carlsson, Boguslaw A. Swedek, Wen-Chiang Tu
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Patent number: 7444812Abstract: A microelectromechanical systems (MEMS) based heat engine capable of converting thermal energy gradients into mechanical or electrical energy, as well as its fabrication process is disclosed. This heat engine design consists of a stressed oscillating beam formed from a shape memory alloy (SMA) thin film. As the temperature of the beam changes, its shape changes due to the phase transformation of the shape memory alloy, causing it to oscillate between a hot source and a cold source. Due to the hysteretic behavior of the phase transformation, the oscillating SMA cantilever beam produces a net mechanical work output that may be either converted to electrical energy or mechanically linked to other MEMS devices.Type: GrantFiled: January 27, 2005Date of Patent: November 4, 2008Inventors: Scott Ryan Kirkpatirck, Azad Siahmakoun, Thomas McDaniel Adams, Zhefu Wang
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Publication number: 20060162331Abstract: A microelectromechanical systems (MEMS) based heat engine capable of converting thermal energy gradients into mechanical or electrical energy, as well as its fabrication process is disclosed. This heat engine design consists of a stressed oscillating beam formed from a shape memory alloy (SMA) thin film. As the temperature of the beam changes, its shape changes due to the phase transformation of the shape memory alloy, causing it to oscillate between a hot source and a cold source. Due to the hysteretic behavior of the phase transformation, the oscillating SMA cantilever beam produces a net mechanical work output that may be either converted to electrical energy or mechanically linked to other MEMS devices.Type: ApplicationFiled: January 27, 2005Publication date: July 27, 2006Inventors: Scott Kirkpatirck, Azad Siahmakoun, Thomas Adams, Zhefu Wang