Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers, a landing structure and a contact structure. The gate layers and the insulating layers are stacked alternatingly, and form stair steps in a staircase region. The landing structure is disposed on a first gate layer of a first stair step of the stair steps in the staircase region. The landing structure includes an upper structure and an isolation stack between the upper structure and the first gate layer. The upper structure is etch-selective to a contact isolation layer that covers the staircase region. The contact structure extends through the contact isolation layer and the landing structure and is connected with the first gate layer of the first stair step.

Abstract: Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

Abstract: The present invention provides a method and system for diagnosing a central nervous system disease, and a composition, and a kit. The diagnosing system comprises: a first detection module, used for detecting a central nervous system-derived marker in a biological body fluid of a subject; a second detection module, used for detecting a central nervous system disease-related marker in the biological body fluid of the subject; and a diagnosis module, diagnosing, on the basis of central nervous system-derived marker and central nervous system disease-related marker detection results respectively obtained by the first detection module and the second detection module, whether the subject suffers from a central nervous system disease.

Abstract: The present disclosure provides a touch screen, a manufacturing method thereof, and a touch display device. The touch screen includes: a substrate; a touch layer and a bonding layer that are on a side of the substrate, the bonding layer being connected to the touch layer by a metal wire; a flexible circuit board connected to the bonding layer; a polarizer on a side of the touch layer away from the substrate and provided with a notch exposing the bonding layer and at least a portion of the metal wire; an insulating light-shielding strip covering the portion of the metal wire exposed by the notch and extending to a side of the polarizer close to the substrate; and a cover plate on a side of the polarizer away from the substrate and including a transparent window area and a shielding area around the transparent window area.

Abstract: A method of fabricating a three-dimensional memory includes forming a laminated structure including stacked dummy gate layers and interlayer insulation layers on one side of a substrate. The respective adjacent dummy gate layers and interlayer insulation layers form staircase stairs. At least a part of the interlayer insulation layer of each of the staircase stairs is exposed. The method also includes forming a buffer layer covering the staircase stairs. The method further includes removing a part of the buffer layer covering the sidewalls of the staircase stairs to form spacing grooves. The method further includes forming a dielectric layer that fills the spacing grooves and covers the staircase stairs. The method further includes forming a contact hole penetrating through the dielectric layer and the buffer layer and extending to the dummy gate layer farthest from the substrate.

Abstract: A method to treat the magnesium surface to manufacture the metallic assembly with the polymer and magnesium to have excellent bonding strength is disclosed. As a method to treat the magnesium surface for the bonded coupling of the mixture of the polymer and magnesium, this is a method including, (a) an etching step, wherein the magnesium surface is treated with an acidic solution; (b) a first surface treatment step, wherein the magnesium surface is treated with ultrasonic waves; (c) a second surface treatment step, wherein the magnesium surface is treated with an acidic solution; (d) a first silane coupling processing step, wherein the magnesium surface is treated with ultrasonic waves; (e) a surface activation treatment step, wherein the magnesium surface is treated with acidic solution; and (f) a second silane coupling processing step, wherein the magnesium surface is treated with ultrasonic waves.

Abstract: A pile-side lateral static load device includes a jack system, a liftable jack cart, a loading jack fixing system, and a loading system. The jack system includes a jack body. The jack system is installed on the liftable jack cart through the loading jack fixing system. The loading system is installed on the loading jack fixing system, and the loading system includes counter-pressure loading systems and counter-tension loading systems. The pile-side lateral static load device has a simple structure, is convenient to install and operate, and can complete lateral loading and in-situ tests under different pile diameters, different tonnages and different precisions, so as to facilitate a simulation test of in-situ lateral loading of a pile.

Abstract: A route determination method, apparatus, server, and storage medium for cold chain distribution, and the method includes: receiving a route determination request from a terminal device, where the route determination request includes: location information of each customer point in a set of customer points to be distributed and location information of a distribution center (21); determining at least one target distribution route according to the location information of each customer point in the set of customer points to be distributed, the location information of the distribution center, scenario constraints and transportation cost constraints (22); and pushing the at least one target distribution route to the terminal device (23).

Abstract: A refrigeration system includes a compressor, a condenser, a throttling device, and an evaporator, which are connected in sequence to form a cooling circuit, the refrigeration system further includes an oil recovery system which includes: an operation chamber, which includes a first port communicating with an oil-containing position in the refrigeration system through a first pipeline, and a second port communicating with a bearing chamber or a bearing lubrication pipeline of the compressor through a second pipeline; and a main piston in the operation chamber, the main piston reciprocating in the operation chamber to perform an extraction stroke and a discharge stroke; in the extraction stroke, an oil-containing refrigerant in the oil-containing position in the refrigeration system is extracted to the operation chamber; and in the discharge stroke, the oil-containing refrigerant in the operation chamber is delivered to the bearing chamber or the bearing lubrication pipeline of the compressor.

Abstract: A method to treat the magnesium surface to manufacture the metallic assembly with the polymer and magnesium to have excellent bonding strength is disclosed. As a method to treat the magnesium surface for the bonded coupling of the mixture of the polymer and magnesium, this is a method including, (a) an etching step, wherein the magnesium surface is treated with an acidic solution; (b) a first surface treatment step, wherein the magnesium surface is treated with ultrasonic waves; (c) a second surface treatment step, wherein the magnesium surface is treated with an acidic solution; (d) a first silane coupling processing step, wherein the magnesium surface is treated with ultrasonic waves; (e) a surface activation treatment step, wherein the magnesium surface is treated with acidic solution; and (f) a second silane coupling processing step, wherein the magnesium surface is treated with ultrasonic waves.

Abstract: A brivaracetam pharmaceutical composition contains an active pharmaceutical ingredient, a matrix forming agent, and a swelling agent. It has a sustained release effect and has a more flat release curve compared with a common gel skeleton sustained-release preparation, and thus achieves the purposes of reducing the release rate of the medicament, controlling the in vivo effective dosage of the medicament, stabilizing the blood concentration, reducing toxic and side effects and reducing the times of daily administration.

Abstract: The present disclosure provides a touch screen, a manufacturing method thereof, and a touch display device. The touch screen includes: a substrate; a touch layer and a bonding layer that are on a side of the substrate, the bonding layer being connected to the touch layer by a metal wire; a flexible circuit board connected to the bonding layer; a polarizer on a side of the touch layer away from the substrate and provided with a notch exposing the bonding layer and at least a portion of the metal wire; an insulating light-shielding strip covering the portion of the metal wire exposed by the notch and extending to a side of the polarizer close to the substrate; and a cover plate on a side of the polarizer away from the substrate and including a transparent window area and a shielding area around the transparent window area.

Abstract: A power converter includes a power stage circuit, a ramp generator circuit, and a control circuit. The power stage circuit is configured to generate an output signal according to an input signal and a control signal. The ramp generator circuit is configured to generate a ramp signal according to the control signal, the input signal, and the output signal. The control circuit is configured to generate the control signal according to the output signal, a reference signal, and the ramp signal.

Abstract: A power stage circuit generates an output signal according to an input signal and a control signal. A ramp generator circuit generates a ramp signal according to the control signal, the input signal, and the output signal. A calculation circuit generates a calculation signal according to the output signal and a reference signal. The calculation circuit operates in a first mode when the power converter operates in a light loading state, and the calculation circuit operates in a second mode when the power converter operates in a normal state. A control circuit generates the control signal according to the calculation signal and the ramp signal. The control circuit includes a comparator circuit and a control signal generator. The comparator circuit generates a comparison signal according to the calculation signal and the ramp signal. The control signal generator generates the control signal according to the comparison signal.

Abstract: Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

Abstract: The present disclosure provides a touch screen, a manufacturing method thereof, and a touch display device. The touch screen includes: a substrate; a touch layer and a bonding layer that are on a side of the substrate, the bonding layer being connected to the touch layer by a metal wire; a flexible circuit board connected to the bonding layer; a polarizer on a side of the touch layer away from the substrate and provided with a notch exposing the bonding layer and at least a portion of the metal wire; an insulating light-shielding strip covering the portion of the metal wire exposed by the notch and extending to a side of the polarizer close to the substrate; and a cover plate on a side of the polarizer away from the substrate and including a transparent window area and a shielding area around the transparent window area.

Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.