Patents by Inventor Zhen Jia Zheng

Zhen Jia Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7022578
    Abstract: A heterojunction bipolar transistor (HBT), and manufacturing method therefor, comprising a semiconductor substrate having a collector region, an intrinsic base region of a compound semiconductive material over the collector region, an extrinsic base region, an emitter structure, an interlevel dielectric layer over the collector region, extrinsic base region and emitter structure, and connections through the interlevel dielectric layer to the base region, the emitter structure, and the collector region. The emitter structure is formed by forming a reverse emitter window over the intrinsic base region, which subsequently is etched to form an emitter window having a multi-layer reverse insulating spacer therein.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: April 4, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Purakh Raj Verma, Shao-fu Sanford Chu, Lap Chan, Jian Xun Li, Zhen Jia Zheng
  • Patent number: 6884712
    Abstract: An integrated circuit, and manufacturing method therefor, is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: April 26, 2005
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Pradeep Yelehanka, Tong Qing Chen, Zhi Yong Han, Zhen Jia Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah