Abstract: The present disclosure relates to methods and apparatus for sharing GPU hardware to generate bin visibility information concurrently for graphics processing. The apparatus can cause a processor to: store, in a GMEM, first data associated with a first graphics processing pass for a first frame of graphics data and second data associated with a second graphics processing pass for a second frame of graphics data. The apparatus can also cause a geometry processor to perform the first graphics processing pass using the first data and a second processor to concurrently perform the second graphics processing pass using the second data such that the first graphics processing pass and the second graphics processing path share the geometry processor. In some aspects, the apparatus can switch the geometry processor from being used for the first graphics processing pass to being used for the second graphics processing pass at a primitive batch boundary.

Abstract: Various embodiments include methods and devices for managing optional commands. Some embodiments may include receiving an optional command from an optional command request device, determining whether the optional command can be implemented, and transmitting, to the optional command request device, an optional command no data response in response to determining that the optional command cannot be implemented.

Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.

Abstract: A MMU may read page descriptors (using virtual addresses as an index) in a burst mode from page tables in a system memory. The page descriptors may include intermediate physical addresses (“IPAs”, in stage 1) and corresponding physical addresses (“PAs”, in stage 2). The virtual address in conjunction with page table base address register is used to index page descriptors into main memory. The MMU may identify a first group of contiguous IPAs beginning at a base IPA and a second group of contiguous IPAs beginning at an offset from the base IPA. The first and second groups may be separated by at least one IPA not contiguous with either the first or second group. The MMU may read a first PA from the page tables that corresponds to the base IPA. The MMU may store an entry in a buffer that includes the PA and a first linearity tag.

Abstract: An apparatus and method are disclosed for transferring data from a first core to a second core of an integrated circuit (IC). The first core includes first and second memory blocks (e.g., first and second portions of a first-in-first-out (FIFO) memory coupled to first and second pre-multiplexers, respectively). The second core includes a multiplexer including first and second inputs coupled to the first and second memory blocks, respectively. Additionally, the second core includes a read controller configured to generate a first read control signal to cause the first and second memory blocks to transfer data to the first and second inputs of the multiplexer, respectively; and generate a second read control signal to cause the multiplexer to transfer data from the first and inputs to an output of the multiplexer.

Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.

Abstract: The aspects include systems and methods of managing virtual memory page shareability. A processor or memory management unit may set in a page table an indication that a virtual memory page is not shareable with an outer domain processor. The processor or memory management unit may monitor for when the outer domain processor attempts or has attempted to access the virtual memory page. In response to the outer domain processor attempting to access the virtual memory page, the processor may perform a virtual memory page operation on the virtual memory page.

Abstract: A mobile phone device comprises the following: a processor; a first display controller for driving an internal display of the mobile phone device; and a second display controller for driving an external display, wherein the external display is connectable to the second display controller via a connector.