Patents by Inventor Zheng Cheng Chen

Zheng Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12014776
    Abstract: A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Cheng Chou, Hsu-Shun Chen, Chien-An Lai, Pei-Ling Tseng, Zheng-Jun Lin
  • Patent number: 7713749
    Abstract: The present invention provides a substrate for protein microarrays, whereby compound A and GPTS are mixed for coating onto a solid support to form a layer, wherein said compound A is selected from a group consisting of nitrocellulose, poly(styrene-co-maleic anhydride) and polyvinylidene fluoride. Moreover, the present invention also provides a protein microarray by depositing proteins on said layer of said substrate.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: May 11, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Li Te Yin, Chao Yun Tsao, Chung We Pan, Su Fung Chiou, Zheng Cheng Chen
  • Patent number: 7419872
    Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: September 2, 2008
    Assignee: Promos Technologies, Inc.
    Inventors: Ching Lee, Chin Wen Lee, Chin Long Hung, Zheng Cheng Chen
  • Publication number: 20080096346
    Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
    Type: Application
    Filed: November 21, 2006
    Publication date: April 24, 2008
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventors: Ching Lee, Chin Wen Lee, Chin Long Hung, Zheng Cheng Chen
  • Publication number: 20060021874
    Abstract: In this present invention it was fabricated to be relates to manufacturing a ceramic interface electrochemical reference electrode for use together with biomedical sensors. Most potentiometric biomedical sensors must have the need to be connected to a reference electrode to offer the readout circuit a stable voltage in the different solutions when measuring for providing that can provide a standard comparing voltage to avoid measuring errors caused by an unstable environment. Usually, However, the presently available commercial reference electrode we used is too big in size and inconvenient to store. For this reason we develop the ceramic interface electrochemical reference electrode which can minimize volume and need not to be preserved in the saturated solution for biosensor. Therefore, the ceramic interface electrochemical reference electrode of the present invention does not need to be stored in solution and can be minimized for use in future sensors.
    Type: Application
    Filed: May 26, 2005
    Publication date: February 2, 2006
    Inventors: Shen-Kan Hsiung, Jung-Chuan Chou, Tai-Ping Sun, Chung-We Pan, Zheng-Cheng Chen
  • Publication number: 20050100969
    Abstract: The present invention provides a substrate for protein microarrays, whereby compound A and GPTS are mixed for coating onto a solid support to form a layer, wherein said compound A is selected from a group consisting of nitrocellulose, poly(styrene-co-maleic anhydride) and polyvinylidene fluoride. Moreover, the present invention also provides a protein microarray by depositing proteins on said layer of said substrate.
    Type: Application
    Filed: October 7, 2004
    Publication date: May 12, 2005
    Applicants: Industrial Technology Research Institute, Co-Wealth Medical Science & Biotechnology INC.
    Inventors: Li-Te Yin, Chao-Yun Tsao, Chung-We Pan, Su-Fung Chiou, Zheng-Cheng Chen