Abstract: This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.

Abstract: This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.

Abstract: A mask design for enhancing line end resolution is provided. In an embodiment, a mask for use in patterning an underlying layer comprises opaque regions and transparent regions arranged to define a line having an end, a slit extending laterally through the line a spaced distance from the end of the line, and a feature extending above or below the space adjacent to the end of the line.

Abstract: MIM capacitors and thin film resistors are fabricated with at least one less lithographic step than the prior art methods. The process step reduction is realized by using semi-transparent metallic electrodes, fabricated with a two-mask process, which provides for direct alignment, and eliminates the need for alignment trenches in an additional layer.

Abstract: A method for forming interconnect dual damascene structures comprising: first, performing a low-k dielectric spin-on; wherein the low-k dielectric is photosensitive and is copper; second, forming trench and vias in the low-k dielectric with a tri-tone mask; and third, applying a liner deposition in the trench and vias; wherein the tri-tone mask comprises a plurality of transmissions, wherein the transmissions of the tri-tone mask is in the range of 0% to 100%. The transmission of the tri-tone mask further comprises a transmission of 0% corresponding to non-erosion regions of the dielectric. Moreover, the transmission of the tri-tone mask further comprises a transmission of 100% corresponding to via regions of the dielectric. Furthermore, the range of 0% to 100% corresponds to trench regions of the dielectric.