Abstract: A connector having a chamber (101) for insertion of a plug includes an optical module (4) having lenses (45) exposed to the chamber for transmitting optical data; and an insulative housing having a receiving slot (115) located behind the chamber (101) and communicating with the chamber for receiving the optical module (4), and a top wall (111) for covering the receiving slot (115). The top wall has a set of openings passing therethrough for exposing key side edges of the receiving slot to exterior.

Abstract: An electrical connector defining a receiving opening for receiving a corresponding plug includes an insulative housing, a number of contacts and an optical module attached to the insulative housing. The insulative housing has a tongue extending into the receiving opening and a cavity behind the receiving opening. Each contact has a retaining portion retained in the insulative housing, a contact portion extending to the tongue, a tail portion and a connecting portion connecting the retaining portion and the tail portion. The optical module is forwardly assembled into the cavity from a rear side of the insulative housing and exposed to the receiving opening. The connecting portions are offset relative to the contact portions of the corresponding contacts in a transverse direction so as to leave said cavity open rearward and allow said optical module to be assembled into the cavity from the rear side of the insulative housing.

Abstract: A novel utility knife in which the parts for securing and replacing the cutting blade are selectively movable in and out of the handle of the knife via a single track system. The blade is secured through a series of elastic metal sheets, one of which contains a projection on a metal tab. The lateral manipulation of the metal tab allows the blade to disengage from the metal sheets. Once disengaged, a user of the utility knife may remove or replace the cutting blade.

Abstract: A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bits 2w-1:w of Y to generate bits 2w-1:w of product Z, and addition of bits 2w-1:w of modulus M to bits 2w-1:w of product Z if the least-significant bit of product Z is 1.

Abstract: A system to process multiplier X and multiplicand Y may include multiplication of a least-significant bit of X and a least-significant w bits of Y to generate a least-significant w bits of product Z. The system may further include determination of whether a least-significant bit of product Z is 1, addition of a least-significant w bits of modulus M to the least-significant w bits of product Z if the least-significant bit of product Z is 1, multiplication of the least-significant bit of X and bits 2w-1:w of Y to generate bits 2w-1:w of product Z, and addition of bits 2w-1:w of modulus M to bits 2w-1:w of product Z if the least-significant bit of product Z is 1.

Abstract: A circuit to convert three input bits (A, B and C) to a redundant format may include a first block with at least one transmission gate, and a second block with at least one static mirror. The first block may receive the three bits and output a sum bit, and the second block may receive the three bits and output a carry bit.

Abstract: Intrinsic variations and challenging leakage control in current bulk-Si MOSFETs force undesired tradeoffs to be made and limit the scaling of SRAM circuits. Circuits and mechanisms are taught herein which improve leakage and noise margin in SRAM cells, such as those comprising either six-transistor (6-T) SRAM cell designs, or four-transistor (4-T) SRAM cell designs. The inventive SRAM cells utilize a feedback means coupling a portion of the storage node to a back-gate of an access transistor. Preferably feedback is coupled in this manner to both access transistors. SRAM cells designed with this built-in feedback achieve significant improvements in cell static noise margin (SNM) without area penalty. Use of the feedback scheme also results in the creation of a practical 4-T FinFET-based SRAM cell that achieves sub-100 pA per-cell standby current and offers similar improvements in SNM as the 6-T cell with feedback.