Patents by Inventor Zheng John Shen
Zheng John Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11670933Abstract: A momentary circuit interrupter in series connection with a mechanical switch to provide protection against short circuit faults in a DC power circuit. The momentary circuit interrupter injects a transient voltage pulse via a pulse transformer to reduce a DC fault current to near zero in a DC circuit branch, thus allowing the mechanical switch to disconnect the faulty branch under a near zero-current condition. The power electronic circuit on the primary side of the transformer controls the discharge of a plurality of pre-charged capacitors to generate the transient voltage pulse during the fault interruption process, but otherwise does not incur any power loss during normal operation. The secondary winding of the pulse transformer conducts the main DC current, and is highly conductive to minimize the conduction power loss.Type: GrantFiled: October 14, 2021Date of Patent: June 6, 2023Assignee: ILLINOIS INSTITUTE OF TECHNOLOGYInventors: Zheng John Shen, Yuanfeng Zhou, Risha Na
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Publication number: 20220123544Abstract: A momentary circuit interrupter in series connection with a mechanical switch to provide protection against short circuit faults in a DC power circuit. The momentary circuit interrupter injects a transient voltage pulse via a pulse transformer to reduce a DC fault current to near zero in a DC circuit branch, thus allowing the mechanical switch to disconnect the faulty branch under a near zero-current condition. The power electronic circuit on the primary side of the transformer controls the discharge of a plurality of pre-charged capacitors to generate the transient voltage pulse during the fault interruption process, but otherwise does not incur any power loss during normal operation. The secondary winding of the pulse transformer conducts the main DC current, and is highly conductive to minimize the conduction power loss.Type: ApplicationFiled: October 14, 2021Publication date: April 21, 2022Applicant: Illinois Institute of TechnologyInventors: Zheng John Shen, Yuanfeng Zhou, Risha Na
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Publication number: 20200203943Abstract: A solid-state circuit breaker and method of use. The circuit breaker includes current and voltage sensors, a power converter, and a digital signal processor. The digital signal processor operates the power converter between three operation states: a first operation state being an on state, a second operation state being an off state, and a third operation state being a current limiting state. The circuit breaker includes an overcurrent detection circuit to detect overcurrent conditions, and turn off the power converter if a load current exceeds a preset threshold. The method of operation includes operating the circuit breaker with a limited amount of overcurrent, and returning the circuit breaker to the normal operation state from the third operation state if the overcurrent condition is removed, or returning the circuit breaker to an off state from the third operation state if the overcurrent condition is sustained.Type: ApplicationFiled: May 31, 2019Publication date: June 25, 2020Applicant: ILLINOIS INSTITUTE OF TECHNOLOGYInventors: Zheng John SHEN, Yuanfeng ZHOU
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Patent number: 9543751Abstract: A solid-state circuit breaker for a DC power system which may operate unidirectional and bidirectional and does not require an external power supply to provide current interruption protection during an event of a short circuit fault.Type: GrantFiled: March 26, 2015Date of Patent: January 10, 2017Assignee: Illinois Institute of TechnologyInventor: Zheng John Shen
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Publication number: 20150280417Abstract: A solid-state circuit breaker for a DC power system which may operate unidirectional and bidirectional and does not require an external power supply to provide current interruption protection during an event of a short circuit fault.Type: ApplicationFiled: March 26, 2015Publication date: October 1, 2015Applicant: Illinois Institute of TechnologyInventor: Zheng John SHEN
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Patent number: 9130462Abstract: A multi-transformer LLC (resonant) power converter having at least two transformers including a first T1 and a second transformer T2 in series includes a switch network configured for receiving input power including a first and second switched node. Resonant circuitry is coupled between the first and second switched node including a series combination of an inductor, a capacitor, a primary winding of T1 and a primary winding of a T2. At least one switch is operable for providing a first mode that includes T2 in the resonant circuitry and a second mode that excludes T2 from the resonant circuitry. Secondary windings of T2 and T1 are connected electrically in parallel for driving an output capacitor (Co) through respective rectifiers which provide conversion from AC to DC.Type: GrantFiled: February 3, 2012Date of Patent: September 8, 2015Assignee: University of Central Florida Research Foundation, Inc.Inventors: Haibing Hu, Xiang Fang, Issa Batarseh, Zheng John Shen
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Patent number: 9099519Abstract: A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region.Type: GrantFiled: May 23, 2012Date of Patent: August 4, 2015Assignee: Great Wall Semiconductor CorporationInventors: Zheng John Shen, Patrick M. Shea, David N. Okada
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Patent number: 8962425Abstract: A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region.Type: GrantFiled: May 23, 2012Date of Patent: February 24, 2015Assignee: Great Wall Semiconductor CorporationInventors: Zheng John Shen, Patrick M. Shea, David N. Okada
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Publication number: 20130313640Abstract: A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Zheng John Shen, Patrick M. Shea, David N. Okada
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Publication number: 20130313633Abstract: A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Zheng John Shen, Patrick M. Shea, David N. Okada
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Publication number: 20130201726Abstract: A multi-transformer LLC (resonant) power converter having at least two transformers including a first T1 and a second transformer T2 in series includes a switch network configured for receiving input power including a first and second switched node. Resonant circuitry is coupled between the first and second switched node including a series combination of an inductor, a capacitor, a primary winding of T1 and a primary winding of a T2. At least one switch is operable for providing a first mode that includes T2 in the resonant circuitry and a second mode that excludes T2 from the resonant circuitry. Secondary windings of T2 and T1 are connected electrically in parallel for driving an output capacitor (Co) through respective rectifiers which provide conversion from AC to DC.Type: ApplicationFiled: February 3, 2012Publication date: August 8, 2013Applicant: University of Central Florida Research Foundation, Inc.Inventors: Haibing Hu, Xiang Fang, Issa Batarseh, Zheng John Shen
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Patent number: 8120153Abstract: A cost-effective, ultra-compact, hybrid power module packaging system and method for making allows device operation in conventional and high temperature ranges over 300° C. Double metal leadframes are directly bonded to the front- and backside of semiconductor chips, and injection-molded high temperature polymer materials encapsulate the module. The invention eliminates the use of unreliable metal wirebonds and solders joints, and expensive aluminum nitride ceramic substrates commonly used in conventional and high temperature hybrid power modules. Advantages of the new power modules include high current carrying capability, low package parasitic impedance, low thermo-mechanical stress under high temperature cycling, low package thermal resistance (double-side cooling), modularity for easy system-level integration, and low-cost manufacturing of devices compatible with current electronic packaging industry. A first embodiment uses molybdenum leadframes for operation in temperatures over 300° C.Type: GrantFiled: September 14, 2006Date of Patent: February 21, 2012Assignee: University of Central Florida Research Foundation, Inc.Inventor: Zheng John Shen
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Patent number: 7719112Abstract: An integrated circuit chip comprising a bond wire and a mass of magnetic material provided on the bond wire, wherein the mass of magnetic material increases the inductance of the bond wire.Type: GrantFiled: August 7, 2007Date of Patent: May 18, 2010Assignee: University of Central Florida Research Foundation, Inc.Inventor: Zheng John Shen
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Publication number: 20080029845Abstract: An integrated circuit chip comprising a bond wire and a mass of magnetic material provided on the bond wire, wherein the mass of magnetic material increases the inductance of the bond wire.Type: ApplicationFiled: August 7, 2007Publication date: February 7, 2008Applicant: UNIVERSITY OF CENTRAL FLORIDA RESEARCH FOUNDATIONInventor: Zheng John Shen
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Patent number: 6972464Abstract: A system of interconnecting regions on an integrated semiconductor device or discrete components. As first connectivity layer has first and second runners to interconnect a plurality of first and second regions. A second connectivity layer has third runners to interconnect the first runners and fourth runners to interconnect the second runners. A third connectivity layer has first pads connected to the third runners and second pads connected to the fourth runners. Solder bumps are used on the first and second pads to connect the pads to other circuits.Type: GrantFiled: June 19, 2003Date of Patent: December 6, 2005Assignee: Great Wall Semiconductor CorporationInventor: Zheng John Shen