Patents by Inventor Zheng-Jun Lin
Zheng-Jun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11495294Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.Type: GrantFiled: November 30, 2020Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng
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Publication number: 20220336016Abstract: A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Chung-Cheng CHOU, Hsu-Shun CHEN, Chien-An LAI, Pei-Ling TSENG, Zheng-Jun LIN
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Patent number: 11442482Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.Type: GrantFiled: September 2, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
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Publication number: 20220254412Abstract: In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.Type: ApplicationFiled: September 9, 2021Publication date: August 11, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chin-I Su, Pei-Ling Tseng, Chung-Cheng Chou
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Patent number: 11393528Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.Type: GrantFiled: February 18, 2021Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Cheng Chou, Chien-An Lai, Hsu-Shun Chen, Zheng-Jun Lin, Pei-Ling Tseng
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Patent number: 11348638Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.Type: GrantFiled: August 24, 2020Date of Patent: May 31, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
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Publication number: 20210407594Abstract: A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.Type: ApplicationFiled: November 24, 2020Publication date: December 30, 2021Inventors: Chin-I SU, Chung-Cheng CHOU, Yu-Der CHIH, Zheng-Jun LIN
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Publication number: 20210241830Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.Type: ApplicationFiled: November 30, 2020Publication date: August 5, 2021Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Pei-Ling Tseng
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Publication number: 20210201994Abstract: A method of forming a filament in a resistive random-access memory (RRAM) device includes applying a cell voltage across a resistive layer of the RRAM device, detecting an increase in a current through the resistive layer generated in response to the applied cell voltage, and in response to detecting the increase in the current, using a first switching device to reduce the current through the resistive layer.Type: ApplicationFiled: March 12, 2021Publication date: July 1, 2021Inventors: Chung-Cheng CHOU, Zheng-Jun LIN, Pei-Ling TSENG
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Publication number: 20210174871Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.Type: ApplicationFiled: February 18, 2021Publication date: June 10, 2021Inventors: Chung-Cheng CHOU, Chien-An LAI, Hsu-Shun CHEN, Zheng-Jun LIN, Pei-Ling TSENG
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Publication number: 20210096586Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.Type: ApplicationFiled: September 2, 2020Publication date: April 1, 2021Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Yu-Der Chih, Chin-I Su
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Patent number: 10950303Abstract: A circuit includes a bias voltage generator and a current limiter. The bias voltage generator is configured to receive a first reference voltage and output a bias voltage responsive to a first current and the first reference voltage. The current limiter is configured to receive a second current at an input terminal, a second reference voltage, and the bias voltage, and, responsive to the second reference voltage and a voltage level of the input terminal, limit the second current to a current limit level, the voltage level of the input terminal being based on the bias voltage.Type: GrantFiled: May 17, 2019Date of Patent: March 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Cheng Chou, Pei-Ling Tseng, Zheng-Jun Lin
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Patent number: 10930344Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.Type: GrantFiled: May 24, 2019Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chung-Cheng Chou, Hsu-Shun Chen, Chien-An Lai, Pei-Ling Tseng, Zheng-Jun Lin
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Publication number: 20200388333Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell.Type: ApplicationFiled: August 24, 2020Publication date: December 10, 2020Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
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Patent number: 10755780Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell. A precharger is configured to selectively precharge the sensing circuit to a predetermined precharge voltage.Type: GrantFiled: February 12, 2019Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Company, LTD.Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng
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Publication number: 20190371397Abstract: A circuit includes a bias voltage generator and a current limiter. The bias voltage generator is configured to receive a first reference voltage and output a bias voltage responsive to a first current and the first reference voltage. The current limiter is configured to receive a second current at an input terminal, a second reference voltage, and the bias voltage, and, responsive to the second reference voltage and a voltage level of the input terminal, limit the second current to a current limit level, the voltage level of the input terminal being based on the bias voltage.Type: ApplicationFiled: May 17, 2019Publication date: December 5, 2019Inventors: Chung-Cheng CHOU, Pei-Ling TSENG, Zheng-Jun LIN
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Publication number: 20190371398Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.Type: ApplicationFiled: May 24, 2019Publication date: December 5, 2019Inventors: Chung-Cheng CHOU, Hsu-Shun CHEN, Chien-An LAI, Pei-Ling TSENG, Zheng-Jun LIN
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Publication number: 20190287612Abstract: A memory device includes a memory cell and a sense amplifier. The sense amplifier has a reference circuit configured to output a reference voltage and a sensing circuit connected to the memory cell. A comparator includes a first input and a second input, with the first input connected to the reference circuit to receive the reference voltage, and the second input connected to the memory cell.Type: ApplicationFiled: February 12, 2019Publication date: September 19, 2019Inventors: Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng