Abstract: A method of operating shared memory in a multiple processor system. A token is by default maintained with a first processor, the token enabling access to shared memory. A determination is made that a second processor requires access to shared memory. A determination is also made as to whether the first processor is accessing to the shared memory. The token is transferred the second processor if the first processor is not accessing the shared memory. The second processor accesses the shared memory with the token.

Abstract: A voltage out-of-calibration detector 200 includes a voltage divider operating between first and second voltage rails and having a plurality of taps 203 for generating first and second comparison voltages. A first set of switches 205 selectively couples at least one of the plurality of taps 203 to the input of a first voltage comparator 401a, first voltage comparator 401a comparing the first comparison voltage with an input voltage and outputing a signal when the input voltage exceeds the first comparison voltage. A second set of switches 206 selectively couples at least one of the plurality of taps 203 to an input of a second voltage comparator 401b, second voltage comparator 401b comparing the second comparison voltage with the input voltage and outputing a signal when the input voltage is below the second comparison voltage. Control logic 300 selectively activates the first and second sets of switches 205/206 in response to received control signals.

Abstract: A method of processing a stream of audio information received by a multiple processor audio decoder. Processing operations are performed by a first processor on the stream of audio information to produce at set of results. The first processor writes the set of results into a shared memory and a flag is set indicating that the results are ready. In response to the flag, a second processor reads the results from shared memory. When the results have been read from shared memory, the second processor sends a command to the first processor. The first processor then clears the flag.

Abstract: A method of exchanging messages between first and second processors. A pending flag in a first register is polled by the first processor and if the flag is in a first selected logic state, a message is written into a second register with the first processor. The pending flag is set to a second selected logic state with the first processor and an interrupt to the second processor is generated. The message is read from the second register with the second processor when the pending flag is in the second logic state. The pending flag set to the first logic state with the second processor.

Abstract: A method of operating a multiple processor device. A first word of a sequence of words is received in a register. A target processor is determined from the first word and the target processor is interrupted. An input ready bit is set and first word from in the register is read with the target processor. A number of words in the sequence to follow the first word determined from the first word. A word counter is set and the input ready bit is cleared with the target processor. The target processor is returned to main code execution.

Abstract: An audio decoder 100 for operating on a received compressed audio data stream compressed using an algorithm employing transform encoding and a bit allocation routine. A first processor 200 performs a first set of operations on the received compressed audio data stream including parsing the compressed audio data stream, recovering data fields within the compressed audio data stream, calculating a bit allocation, and passing frequency domain coefficients to shared memory. A second digital signal processor 100b performs a second set of operations on data passed from the first digital signal processor to shared memory including performing inverse transform operations on the data passed from the first digital signal processor.

Abstract: A message is transferred from external device through a first processor and from the first processor to a second processor. A check is made that the message passed to the second processor without error. The message is interpreted by a selected one of the first and second processors. Boot operations are performed by the selected processor in response to the interpretation of the message.