Abstract: A method of performing co-integrated fabrication of a non-volatile memory (NVM) and a gate-all-around (GAA) nanosheet field effect transistor (FET) includes recessing fins in a channel region of the NVM and the FET to form source and drain regions adjacent to recessed fins, and removing alternating portions of the recessed fins of the NVM and the FET to form gaps in the recessed fins. A stack of layers that make up an NVM structure are conformally deposited within the gaps of the recessed fins leaving second gaps, smaller than the gaps, and above the recessed fins of the NVM while protecting the FET with the organic planarization layer (OPL) and a block mask. The OPL and block mask are removed from the FET, and another OPL and another block mask protect the NVM while a gate of the FET is formed above the recessed fins and within the gaps.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Abstract: A method is presented for forming a nanowire electrode. The method includes forming a plurality of nanowires over a first substrate, depositing a conducting layer over the plurality of nanowires, forming solder bumps and electrical interconnections over a second flexible substrate, and integrating nanowire electrode arrays to the second flexible substrate. The plurality of nanowires are silicon (Si) nanowires, the Si nanowires used as probes to penetrate skin of a subject to achieve electrical biopotential signals. The plurality of nanowires are formed over the first substrate by metal-assisted chemical etching.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Abstract: A light source system, comprising: a wavelength conversion layer (102, 202) used for receiving exciting light (L3) and generating excited light (L2); a transparent thermal conduction substrate (104, 204) used for supporting the wavelength conversion layer (102, 202), and an excitation light source which emits the exciting light (L3) from a side of the wavelength conversion layer (102, 202) to the wavelength conversion layer (102, 202); and a red light source which emits red light (L1) from a side of the transparent thermal conduction substrate (104, 204) to the wavelength conversion layer (102, 202). The light source system can effectively solve the problem of insufficient red light in fluorescent powder excitation technology.

Abstract: A dual-unlock combination lock provides a first set of correct password and a second set of correct password to be used independently. After a password switch pushbutton is operated to drive a bracket to a corresponding position, a corresponding correct password is input into a combination wheel, so that an elastic member props the bracket to release from a transmission element in order to unlock the combination lock. One password element can achieve the effect of unlocking the lock by using two sets of correct password independently to provide a broader scope of applicability. The first set of correct password with the setting and use similar to those of a common password is provided for ordinary users, and the second set of correct password is a fixed code provided for designated users to unlock the combination lock by scanning an identification code by a mobile terminal.

Abstract: A semiconductor structure is provided. The structure includes a RRAM cell having a first end and a second end. The second end is connected to a first potential. The structure includes a decoupling capacitor having a first end connected in series with the first end of the RRAM cell and a second end connected to a second potential. The structure includes a FET arranged across the capacitor to form a bridged capacitor by having a FET source connected to the first end of the capacitor and a FET drain connected to the second end of the capacitor. A paired activation and subsequent deactivation of the FET enables a short protection mode of the capacitor that provides a series resistance above a threshold amount, between the second potential and the first end of the RRAM cell, responsive to a detected short of the capacitor from the supply to the first potential.

Abstract: A pair of vertical fin field effect transistors (FinFETs) having different gate lengths, includes, a first bottom source/drain on a first region of a substrate, wherein the first bottom source/drain includes a first tier having a first height adjacent to a first vertical fin and a second tier having a second height greater than the first tier removed from the first vertical fin; and a second bottom source/drain on a second region of the substrate, wherein the second bottom source/drain includes a third tier having a third height adjacent to a second vertical fin and a fourth tier having a fourth height greater than the third tier removed from the second vertical fin, wherein the third height is less than the first height and the fourth height is equal to the second height.

Abstract: Innovations in unified intra block copy (“BC”) and inter prediction modes are presented. In some example implementations, bitstream syntax, semantics of syntax elements and many coding/decoding processes for inter prediction mode are reused or slightly modified to enable intra BC prediction for blocks of a frame. For example, to provide intra BC prediction for a current block of a current picture, a motion compensation process applies a motion vector that indicates a displacement within the current picture, with the current picture being used as a reference picture for the motion compensation process. With this unification of syntax, semantics and coding/decoding processes, various coding/decoding tools designed for inter prediction mode, such as advanced motion vector prediction, merge mode and skip mode, can also be applied when intra BC prediction is used, which simplifies implementation of intra BC prediction.

Abstract: Provided are a GLP-1(7-37) polypeptide analogue, a fatty acid-modified derivative of the analogue, and a medicament comprising the derivative. Further, also provided are a preparation method of the derivative, and use of the same in the preparation of a medicament.

Abstract: The present disclosure discloses a resistive sub-module hybrid MMC and a direct current fault processing strategy thereof. The hybrid MMC prevents fault current from entering a direct current system from the alternating current side by artificially creating three-phase earthing short circuit on the alternating current side of a converter during the direct current fault processing process, and can reduce the number of required power electronic devices compared with the module hybrid MMC. At the same time, the direct current fault processing speed of the hybrid MMC is fast, and the duration of the artificially creating three-phase short circuit fault in the fault processing process is less than 60 ms, which will not have a great impact on the alternating current system. The present disclosure greatly reduces the cost of building an overhead line high-voltage flexible direct current transmission system, and has very strong reference significance and use value in engineering.

Abstract: Innovations in unified intra block copy (“BC”) and inter prediction modes are presented. In some example implementations, bitstream syntax, semantics of syntax elements and many coding/decoding processes for inter prediction mode are reused or slightly modified to enable intra BC prediction for blocks of a frame. For example, to provide intra BC prediction for a current block of a current picture, a motion compensation process applies a motion vector that indicates a displacement within the current picture, with the current picture being used as a reference picture for the motion compensation process. With this unification of syntax, semantics and coding/decoding processes, various coding/decoding tools designed for inter prediction mode, such as advanced motion vector prediction, merge mode and skip mode, can also be applied when intra BC prediction is used, which simplifies implementation of intra BC prediction.

Abstract: A method is presented for incorporating skip vias in a place and route flow of an integrated circuit design. The method includes employing a place and route tool to add the skip vias, each skip via extending through a metallization layer to electrically connect a metal layer above the metallization layer to a metal layer below the metallization layer and, when a violation of a design rule is detected due to the addition of one or more of the skip vias, substituting skip vias that violate the design rule with a standard via.

Abstract: A method forms an air gap metal tip structure for (ESD) protection. The method forms an air chamber, from an upper substrate and a lower substate disposed below the upper substrate, within which a first metal tip and a second metal tip are disposed. The first and second metal tips are disposed along at least one horizontal axis parallel to the upper and lower substrates. The chamber includes a portion between points of the metal tips, such that oxygen trapped in the chamber is converted into ozone responsive to an arc between the metal tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an arc absence between the metal tips to maintain the ESD protection for subsequent arcs. An under fill level is disposed between the lower and upper substrates, and above one or more layers having the first and second metal tips.

Abstract: An air gap metal tip structure is provided for (ESD) protection. The structure includes first and second metal tips disposed along at least one horizontal axis that is parallel to a upper substrate and a lower substrate. The structure includes an air chamber formed between the upper and lower substrate within which the first metal tip and the second metal tip are disposed. The air chamber includes a portion between points of the metal tips. The structure includes an under fill level disposed between the lower and upper substrates, and above one or more layers having the metal tips. Oxygen trapped in the air chamber is converted into ozone responsive to an arc between the metal tips to dissipate the arc, and the ozone is decomposed back into the oxygen responsive to an absence of the arc between the metal tips to maintain the ESD protection for subsequent arcs.

Abstract: RRAM devices with tunable forming voltage are provided herein. A method of forming an RRAM device includes: depositing a first dielectric layer on a substrate; forming metal pads in the first dielectric layer; depositing a capping layer onto the first dielectric layer; forming heating elements in the capping layer in contact with the metal pads; forming an RRAM stack on the capping layer; patterning the RRAM stack into an RRAM cell(s) including a bottom electrode, a high-? switching layer disposed on the bottom electrode, and a top electrode disposed on the high-? switching layer; depositing a second dielectric layer over the RRAM cell(s); and forming a contact to the top electrode in the second dielectric layer. An RRAM device and a method of operating an RRAM device are also provided.

Abstract: One embodiment can provide an intelligent robotic system. The intelligent robotic system can include at least one multi-axis robotic arm, at least one gripper attached to the multi-axis robotic arm for picking up a component, a machine vision system comprising at least a three-dimensional (3D) surfacing-imaging module for detecting 3D pose information associated with the component, and a control module configured to control movements of the multi-axis robotic arm and the gripper based on the detected 3D pose of the component.

Abstract: A semiconductor structure is provided. The structure includes a RRAM cell having a first end and a second end. The second end is connected to a first potential. The structure includes a decoupling capacitor having a first end connected in series with the first end of the RRAM cell and a second end connected to a second potential. The structure includes a FET arranged across the capacitor to form a bridged capacitor by having a FET source connected to the first end of the capacitor and a FET drain connected to the second end of the capacitor. A paired activation and subsequent deactivation of the FET enables a short protection mode of the capacitor that provides a series resistance above a threshold amount, between the second potential and the first end of the RRAM cell, responsive to a detected short of the capacitor from the supply to the first potential.

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer, forming a plurality of mandrel lines over the dielectric layer, and forming a plurality of non-mandrel lines over the dielectric layer between adjacent ones of the mandrel lines utilizing self-aligned double patterning. The method also includes forming at least one spacer-merge region extending from a first portion of a first one of the mandrel lines to a second portion of a second one of the mandrel lines in a first direction and covering at least a portion of one or more of the non-mandrel lines between the first mandrel and the second mandrel in a second direction orthogonal to the first direction. The method further includes forming a plurality of trenches in the dielectric layer by transferring a pattern of (i) the mandrel lines and (ii) portions of the non-mandrel lines outside the at least one spacer-merge region.

Abstract: One embodiment can provide a machine-vision system. The machine-vision system can include a structured-light projector, a first camera positioned on a first side of the structured-light projector, and a second camera positioned on a second side of the structured-light projector. The first and second cameras are configured to capture images under illumination of the structured-light projector. The structured-light projector can include a laser-based light source.