Abstract: The present disclosure provides a successive approximation method of three-state quantization and a successive approximation analog-to-digital converter circuit. The method includes for a first successive approximation of the arbitrary analog input signal between 0 and 1, comparing it with a quantization line 1/2; performing a second successive approximation according to a state of the first successive approximation; and by analogy up to a Nth successive approximation, in case that a certain successive approximation is the state three during the comparison process, ending the approximation, indicating that the interval where the signal is located has been found.

Abstract: The disclosure relates to a table (100). The table (100) has a table top (102), a plurality of legs (104) connectable to the table top (102), and an air purifier (106) adapted to be placed below the table top (102). A bottom side of the table top (102) is provided with at least one groove (112) extending in a circumferential direction for preventing liquid from traveling from an outer edge of the table top (102) along the bottom side of the table top (102) and reaching an inner section of the air purifier (106). The disclosure also relates to a method for purifying air using a table (100).

Abstract: Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.

Abstract: Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

Abstract: Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.

Abstract: Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

Abstract: Systems, methods, and apparatus for improving bus latency are described. A data communication apparatus has an interface circuit adapted to couple the apparatus to a first serial bus, a clock source configured to provide a clock signal and a trigger handler. The interface circuit may be configured to receive trigger configuration information in a first transaction conducted over a serial bus, and receive a trigger actuation command from a bus master coupled to the serial bus. The trigger handler may be configured to delay a trigger actuation signal for a delay duration defined by the trigger configuration information, and provide the trigger actuation signal after the delay duration has expired. The trigger actuation signal may be generated in response to the trigger actuation command.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: Systems, methods, and apparatus for functionally extending a capability of a write datagram for RFFE and SPMI devices are provided. A sending device sets a configuration register to indicate an operation mode of a write command and generates a command code field in the write command. A most significant bit of the command code field has a value of 1 and remaining bits of the command code field are defined based on the operation mode. The sending device further includes payload bytes in a payload field of the write command based on the operation mode and sends the write command to a receiver via a bus interface. The sending device may also set a page-address register to include a page-address to be used if page segmented access (PSA) is enabled for the write command and set the configuration register to indicate whether the PSA for the write command is enabled.

Abstract: A circuit including a radio frequency (RF) amplifier including a transistor configured to receive an RF signal at its control terminal, a capacitor coupled to a first terminal of the transistor, an inductor coupled to a second terminal of the transistor, wherein the capacitor and inductor form a loop from the first terminal to the second terminal, wherein the loop bypasses a parasitic inductance between the second terminal and ground.

Abstract: Systems, methods, and apparatus for sharing a serial bus interface among devices having different operating speeds are described. A sequence of commands on a data line of the serial bus are generated including a start condition signal and a device identifier signal where the identifier signal is part of a command frame in the sequence of commands. The sequence of commands is transmitted on the data line concurrent with the transmission of a clock signal on a clock line of the serial bus during the duration of the device identifier signal. The frequency of the clock signal is set at a first clock frequency for the duration of the device identifier signal where the first clock frequency is a frequency supported among all devices coupled to the serial bus, allowing all devices to decode an initial sequence, whether the devices are configured for higher frequency operation or not.

Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for operating a power amplifier. In one example, the apparatus includes a power amplifier configured to amplify an input signal having a frequency to produce a radio frequency (RF) output signal at an output and a harmonic tuning circuit coupled between a power supply and the power amplifier output, the harmonic tuning circuit configured to reduce a current or voltage provided to the power amplifier via a resonance at one or more harmonics of the frequency of the input signal.

Abstract: Systems, methods, and apparatus for functionally extending a capability of a write datagram for RFFE and SPMI devices are provided. A sending device sets a configuration register to indicate an operation mode of a write command and generates a command code field in the write command. A most significant bit of the command code field has a value of 1 and remaining bits of the command code field are defined based on the operation mode. The sending device further includes payload bytes in a payload field of the write command based on the operation mode and sends the write command to a receiver via a bus interface. The sending device may also set a page-address register to include a page-address to be used if page segmented access (PSA) is enabled for the write command and set the configuration register to indicate whether the PSA for the write command is enabled.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for operating a power amplifier. In one example, the apparatus includes a power amplifier configured to amplify an input signal having a frequency to produce a radio frequency (RF) output signal at an output and a harmonic tuning circuit coupled between a power supply and the power amplifier output, the harmonic tuning circuit configured to reduce a current or voltage provided to the power amplifier via a resonance at one or more harmonics of the frequency of the input signal.

Abstract: Systems, methods, and apparatus for managing digital communication interfaces coupled to data communication links are disclosed. In one example, the digital communication interfaces provide methods, protocols and techniques that may be used to provide a common slew rate for signals transmitted on a communication link that may be operated at multiple different voltage ranges. A method may include determining a first voltage range defined for transmitting signals over the communication link when the over the communication link is operated in a first mode of operation, configuring a line driver to operate within the first voltage range with a common slew rate that applies to each of a plurality of modes of operation, and transmitting first data over the communication link in one or more signals that switch within the first voltage range with the common slew rate. Each mode of operation may define a different voltage range for transmitting signals.

Abstract: Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.

Abstract: Methods and apparatuses are described that facilitate data communication across a serial bus. In one configuration, a transmitter configures a plurality of devices by assigning one or more trigger registers to each device of the plurality of devices and sends to each device a trigger register assignment command indicating a trigger register assigned to a device and identifying a trigger corresponding to the device. The transmitter then addresses a packet to an assigned trigger register and generates a bit-index field in the packet. Bits in the bit-index field respectively represent triggers corresponding to devices associated with the assigned trigger register, wherein each bit indicates whether one or more corresponding devices are enabled for operation. The transmitter then sends the packet to the plurality of devices via the serial bus.