Abstract: The present application discloses a signal processing method and an apparatus, which are used to achieve signal compensation on the basis of a relative group delay, and to improve the precision of TOA estimation, thereby finally improving the positioning precision of UE. The signal processing method provided in the present application comprises: performing channel estimation processing on the basis of a received positioning reference signal (PRS), to obtain a frequency domain channel response; determining a difference value of a relative group delay of a sub-band on the basis of the frequency domain channel response; and compensating, on the basis of the difference value of the relative group delay of the sub-band, a locally received PRS or the frequency domain channel response; or reporting the difference value of the relative group delay of the sub-band to a transmitting end, and compensating a transmission signal by means of the transmitting end.

Abstract: A light emitting substrate, a method of driving a light emitting substrate, and a display device are provided. The light emitting substrate includes a plurality of light emitting units arranged in an array. Each light emitting unit includes a driving circuit, a plurality of light emitting elements, and a driving voltage terminal. The plurality of light emitting elements are sequentially connected in series and connected between the driving voltage terminal and the output terminal of the driving circuit. The driving circuit is configured to output a relay signal through the output terminal in a first period according to a first input signal received by the first input terminal and a second input signal received by the second input terminal, and supply a driving signal to the plurality of light emitting elements sequentially connected in series through the output terminal in a second period.

Abstract: A light emitting substrate is provided. The light emitting substrate includes at least one light emitting controlling unit. The at least one light emitting controlling unit includes a plurality of light emitting elements arranged in M rows and N columns and grouped into (P×Q) number of sub-units, M being an integer equal to or greater than one, N being an integer equal to or greater than one, P being an integer equal to or greater than one, and Q being an integer equal to or greater than one; P groups of first voltage signal lines; and Q groups of second voltage signal lines. The (P×Q) number of sub-units are arranged in P rows and Q columns. A respective sub-unit in a p-th row and a q-th column includes K columns of light emitting elements, K being an integer equal to or greater than one.

Abstract: A display panel and a display apparatus. The display panel includes: a substrate; a light-emitting layer, and a low refractive index film layer and a high refractive index film layer. The light-emitting layer includes a plurality of light-emitting units arranged at intervals and a pixel definition block arranged between adjacent light-emitting units. The low refractive index film layer and the high refractive index film layer are arranged on the side of the light-emitting layer. The low refractive index film layer includes a plurality of microstructures, and the high refractive index film layer covers at least a part of surfaces of the microstructures. The orthographic projections of the microstructures on the light-emitting layer cover the light-emitting units in corresponding positions. In the thickness direction of the display panel, a plurality of total internal reflection interfaces are formed between the microstructures and the high refractive index film layer.

Abstract: A display panel and a production method thereof. A display panel includes an array substrate, a first electrode layer, an organic functional layer, and a second electrode layer, which are stacked. The first electrode layer includes at least one electrode block, and the second electrode layer is connected with at least one auxiliary electrode. The auxiliary electrode is located on the array substrate or located in the array substrate. The auxiliary electrode includes a first material layer, and the first material layer includes a bottom surface facing the array substrate, and a side surface intersecting the bottom surface of the first material layer, an angle between the bottom surface of the first material layer and the side surface of the first material layer is greater than or equal to 60° and less than or equal to 160°.

Abstract: A light emitting substrate is provided. The light emitting substrate includes at least one light emitting controlling unit. The at least one light emitting controlling unit includes a plurality of light emitting elements arranged in M rows and N columns and grouped into (P×Q) number of sub-units, M being an integer equal to or greater than one, N being an integer equal to or greater than one, P being an integer equal to or greater than one, and Q being an integer equal to or greater than one; P groups of first voltage signal lines; and Q groups of second voltage signal lines. The (P×Q) number of sub-units are arranged in P rows and Q columns. A respective sub-unit in a p-th row and a q-th column includes K columns of light emitting elements, K being an integer equal to or greater than one.

Abstract: The present disclosure discloses a display panel and a display device. The display panel includes: a base substrate, including a plurality of substrate via holes located in a display area of the display panel; and a plurality of driving signal lines and a plurality of bonding terminals, respectively located on different sides of the base substrate. At least one of the plurality of driving signal lines is electrically connected to at least one of the plurality of bonding terminals through the substrate via hole(s).

Abstract: A shift register (SR) includes a voltage control circuit (110) and a bias compensation circuit (120). The voltage control circuit (110) is configured to control a voltage at a first node (Output) to be a first voltage or a second voltage. The bias compensation circuit (120) is configured to: when the voltage at the first node (Output) is the first voltage, transmit a first signal received by a first signal terminal (VDD-A) to a first signal output terminal (EM1), and transmit a second signal received by a second signal terminal (VDD-B) to a second signal output terminal (EM2); and in response to the voltage at the first node (Output) being the second voltage, transmit a signal received by a first voltage terminal (LVGL1) to the first signal output terminal (EM1) and the second signal output terminal (EM2).

Abstract: A pixel circuit includes a plurality of driving transistors and a plurality of gating sub-circuits. The plurality of driving transistors are configured to output different driving currents under control of a received control signal. Each gating sub-circuit is electrically connected to a respective selection signal terminal, a scanning signal terminal, a respective driving transistor and a light-emitting device, and is configured to be turned on under control of a scanning signal from the scanning signal terminal and a selection signal from the selection signal terminal to transmit a driving current from the connected driving transistor to the light-emitting device. Within a frame period, one of a plurality of selection signal terminals respectively electrically connected to the plurality of gating sub-circuits outputs a selection signal.

Abstract: A method for controlling an asynchronous induction motor, a control device for implementing the method, a motor system including the control device, and a computer-readable storage medium on which a computer program for implementing the method is stored. The method for controlling the asynchronous induction motor includes: A. determining a target value of d-axis current according to a target value of q-axis current of the asynchronous induction motor; B. determining a correction value of the target value of the d-axis current based on q-axis voltage and d-axis voltage of the asynchronous induction motor; and C. determining target values of the d-axis voltage and the q-axis voltage of the asynchronous induction motor based on the correction value of the target value of the d-axis current and the target value of the q-axis current.

Abstract: Provided are a photoelectric detection circuit and a driving method thereof, a display apparatus and a manufacturing method thereof. The photoelectric detection circuit includes: a first reset sub-circuit, a second reset sub-circuit, a first storage sub-circuit, a data read sub-circuit and a photosensitive device. A first terminal of the data read sub-circuit, a first terminal of the first storage sub-circuit, a first electrode of the photosensitive device and a first terminal of the first reset sub-circuit are connected to a first node. A second electrode of the photosensitive device is connected to a common voltage line. The data read sub-circuit is configured to transmit a voltage of the first node to a data read line in response to a signal of a scan line. The first reset sub-circuit is configured to reset the voltage of the first node.

Abstract: The present disclosure discloses a display panel and a display device. The display panel includes: a base substrate, including a plurality of substrate via holes located in a display area of the display panel; and a plurality of driving signal lines and a plurality of bonding terminals, respectively located on different sides of the base substrate. At least one of the plurality of driving signal lines is electrically connected to at least one of the plurality of bonding terminals through the substrate via hole(s).

Abstract: The present disclosure provides a pixel driving circuit and a display panel. The pixel driving circuit includes: a data writing sub-circuit configured to transmit a data voltage signal to a first terminal of a driving sub-circuit in response to a first scanning signal; a threshold compensation sub-circuit configured to compensate for a threshold voltage of the driving sub-circuit in response to a second scanning signal; a storage sub-circuit configured to store the data voltage signal; the driving sub-circuit configured to provide a driving current for a light emitting device to be driven according to voltages of a first terminal and a control terminal of the driving sub-circuit; and a voltage maintaining sub-circuit configured to maintain the voltage of the control terminal of the driving sub-circuit when the voltage of the first terminal of the driving sub-circuit jumps.

Abstract: A light-emitting substrate and a display device are provided. Each light-emitting unit includes a first voltage terminal. The first voltage line includes a first portion, a first connecting portion, and a second portion. The first portion is electrically connected with first voltage terminals of a first row to a Y-th row of light-emitting units in a corresponding column. An extension direction of a second portion of the first voltage line has an included angle with both the first direction and the second direction. The first connecting portion is at boundary of the Y-th row and a (Y+1)-th row of light-emitting units. The first transmission line is electrically connected with first voltage terminals of the (Y+1)-th row to an N-th row of light-emitting units in a corresponding column, and is electrically connected with the first connecting portion of the first voltage line corresponding to light-emitting units of a corresponding column.

Abstract: A superconducting magnet system having two-stage quenching. A primary coil assembly includes a coil section configured to be superconducting when conducting current below a first critical current. An EMI shielding coil assembly includes a coil section configured to be superconducting when conducting current below a second critical current, which is electrically coupled to a variable resistor configured to be superconducting when conducting current below a third critical current and to be non-superconducting when conducting current at or above the third critical current that is less than both the first and second critical currents. Generating a magnetic flux within the EMI shielding coil assembly causes the current conducted through the variable resistor to exceed the third critical current, quenching the variable resistor and generating heat. The EMI shielding coil assembly is disposed such that the heat from the variable resistor quenches the primary coil assembly.

Abstract: Embodiments of the present disclosure provide a method and apparatus for correcting a Tx delay, and a storage medium. The method includes receiving Tx delay (Tx Delay) parameter information transmitted by a transmitting node, and transmitting positioning reference signal configuration information to a receiving node; and correcting a positioning measurement value on the basis of the Tx Delay parameter information, the positioning measurement value being obtained by means of the receiving node measuring, according to the positioning reference signal configuration information, a positioning reference signal transmitted by the transmitting node. In the embodiments of the present disclosure, by using Tx Delay parameter information, the effect of a Tx delay on a time-related positioning measurement value can be eliminated, and the positioning precision is effectively improved.

Abstract: Disclosed are a downlink positioning reference signal receiving and transmitting method, and a terminal, a base station, a device and an apparatus. The method includes: in response to receiving SPS DL-PRS configuration information of a plurality of base stations configured by a LMF via SPS, receiving SPS DL-PRS activation information of the plurality of base stations; where the plurality of base stations comprise a serving base station and a non-serving base station; receiving and measuring an SPS DL-PRS according to a period and time-frequency resource information of the SPS DL-PRS determined from the SPS DL-PRS configuration information and according to a downlink slot of the SPS DL-PRS determined from the SPS DL-PRS activation information, and obtaining a positioning measurement; and sending the positioning measurement to the LMF or the serving base station of the UE.

Abstract: A pixel circuit includes a current control sub-circuit, a combined light emitting sub-circuit, and a first light emitting element to an Nth light emitting element, N being a natural number greater than 1. The current control sub-circuit is configured to receive a display data signal and a light emitting control signal, control whether to generate a driving current according to the light emitting control signal, and control a current intensity of the generated driving current according to the display data signal. The combined light emitting sub-circuit is configured to receive the driving current and a first light emitting data signal to an Nth light emitting data signal and drive one or more of the first light emitting element to the Nth light emitting element to emit light according to the first light emitting data signal to the Nth light emitting data signal.

Abstract: An array substrate includes M pixel lines and N pixel circuit groups. The M pixel lines are disposed in a display area and arranged in a first direction. The N pixel circuit groups are arranged in the first direction. M is an integer greater than or equal to 2, and N is a positive integer less than M. A pixel circuit group of the N pixel circuit groups is electrically connected to adjacent two pixel lines of the M pixel lines, and the first direction is one of a row direction and a column direction.

Abstract: Disclosed are a positioning method and apparatus, which are used for eliminating a clock skew between base stations and improving the UE positioning accuracy of an UL-TDOA/DL-TDOA positioning technical scheme. The method comprises: determining positioning reference signal configuration information; for a downlink time difference of arrival (DL-TDOA) positioning technical scheme, receiving and measuring downlink positioning reference signals from different base stations on the basis of the positioning reference signal configuration information, determining downlink positioning measurement quantity information, and reporting the downlink positioning measurement quantity information and location information of a reference terminal; and for an uplink time difference of arrival (UL-TDOA) positioning technical scheme, sending an uplink positioning reference signal on the basis of the positioning reference signal configuration information, and sending the location information of the reference terminal.