Patents by Inventor Zhi-Cheng Lee
Zhi-Cheng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240047554Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.Type: ApplicationFiled: August 30, 2022Publication date: February 8, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Huai-Tzu Chiang, Chuang-Han Hsieh, Kai-Lin Lee
-
Publication number: 20240021702Abstract: An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.Type: ApplicationFiled: August 11, 2022Publication date: January 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Huai-Tzu Chiang, Kai-Lin Lee
-
Publication number: 20230402537Abstract: A high electron mobility transistor (HEMT) device includes a substrate, a channel layer, a source, a drain, a buffer layer, and a plurality of amorphous regions. The channel layer is located above the substrate. The source is located on the channel layer. The drain is located on the channel layer. The buffer layer is located between the substrate and the channel layer. The plurality of amorphous regions are located in the buffer layer below the source and the drain.Type: ApplicationFiled: July 13, 2022Publication date: December 14, 2023Applicant: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Kai Lin Lee, Zhi-Cheng Lee, Chuang-Han Hsieh
-
Publication number: 20230361207Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
-
Patent number: 11749748Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.Type: GrantFiled: July 6, 2021Date of Patent: September 5, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
-
Patent number: 11715784Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.Type: GrantFiled: May 26, 2022Date of Patent: August 1, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
-
Publication number: 20230238450Abstract: A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.Type: ApplicationFiled: March 31, 2023Publication date: July 27, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
-
Patent number: 11652154Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.Type: GrantFiled: August 15, 2021Date of Patent: May 16, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
-
Publication number: 20230102936Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.Type: ApplicationFiled: November 1, 2021Publication date: March 30, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Chuang-Han Hsieh, Kai-Lin Lee
-
Patent number: 11610973Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.Type: GrantFiled: December 28, 2021Date of Patent: March 21, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
-
Patent number: 11527652Abstract: A semiconductor structure includes at least one stacked fin structure, a gate and a source/drain. At least one stacked fin structure is located on a substrate, wherein the stacked fin structure includes a first fin layer and a second fin layer, and a fin dielectric layer is sandwiched by the first fin layer and the second fin layer. The gate is disposed over the stacked fin structure. The source/drain is disposed directly on the substrate and directly on sidewalls of the whole stacked fin structure. The present invention provides a semiconductor process formed said semiconductor structure.Type: GrantFiled: November 3, 2020Date of Patent: December 13, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
-
Publication number: 20220285522Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.Type: ApplicationFiled: May 26, 2022Publication date: September 8, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
-
Patent number: 11380777Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.Type: GrantFiled: November 23, 2020Date of Patent: July 5, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
-
Publication number: 20220165864Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.Type: ApplicationFiled: November 23, 2020Publication date: May 26, 2022Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
-
Publication number: 20220123121Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.Type: ApplicationFiled: December 28, 2021Publication date: April 21, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
-
Patent number: 11251279Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.Type: GrantFiled: July 23, 2020Date of Patent: February 15, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
-
Patent number: 11239327Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.Type: GrantFiled: July 16, 2019Date of Patent: February 1, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
-
Publication number: 20220013648Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. Agate dielectric layer is disposed under the metal compound layer and contacts the substrate.Type: ApplicationFiled: July 23, 2020Publication date: January 13, 2022Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
-
Publication number: 20210376121Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.Type: ApplicationFiled: August 15, 2021Publication date: December 2, 2021Applicant: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
-
Publication number: 20210336044Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen