Patents by Inventor Zhibin Ren
Zhibin Ren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080171426Abstract: A method for achieving uniaxial strain on originally biaxial-strained thin films after uniaxial strain relaxation induced by ion implantation is provided. The biaxial-strained thin film receives ion implantation after being covered by a patterned implant block structure. The strain in the uncovered region is relaxed by ion implantation, which induces the lateral strain relaxation in the covered region. When the implant block structure is narrow (dimension is comparable to the film thickness), the original biaxial strain will relax uniaxially in the lateral direction.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhibin Ren, Katherine L. Saenger, Haizhou Yin
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Patent number: 7396776Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: GrantFiled: July 10, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Patent number: 7384851Abstract: A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.Type: GrantFiled: July 15, 2005Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: MeiKei Ieong, Zhibin Ren, Haizhou Yin
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Patent number: 7374998Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.Type: GrantFiled: February 3, 2006Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: John Michael Hergenrother, Zhibin Ren, Dinkar Virendra Singh, Jeffrey William Sleight
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Patent number: 7326997Abstract: A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.Type: GrantFiled: November 17, 2006Date of Patent: February 5, 2008Assignee: International Business Machines CorporationInventors: Huilong Zhu, Jing Wang, Bruce B. Doris, Zhibin Ren
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Publication number: 20080014740Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: ApplicationFiled: July 10, 2006Publication date: January 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Publication number: 20070257315Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.Type: ApplicationFiled: May 4, 2006Publication date: November 8, 2007Applicant: International Business Machines CorporationInventors: Stephen Bedell, Joel De Souza, Zhibin Ren, Alexander Reznicek, Devendra Sadana, Katherine Saenger, Ghavam Shahidi
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Publication number: 20070184619Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.Type: ApplicationFiled: February 3, 2006Publication date: August 9, 2007Inventors: John Hergenrother, Zhibin Ren, Dinkar Singh, Jeffrey Sleight
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Publication number: 20070120197Abstract: A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.Type: ApplicationFiled: November 17, 2006Publication date: May 31, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huilong Zhu, Jing Wang, Bruce Doris, Zhibin Ren
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Publication number: 20070122961Abstract: A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.Type: ApplicationFiled: November 17, 2006Publication date: May 31, 2007Applicant: International Business Machines CorporationInventors: Huilong Zhu, Jing Wang, Bruce Doris, Zhibin Ren
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Patent number: 7183613Abstract: A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.Type: GrantFiled: November 15, 2005Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Huilong Zhu, Jing Wang, Bruce B. Doris, Zhibin Ren
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Publication number: 20070020867Abstract: A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.Type: ApplicationFiled: July 15, 2005Publication date: January 25, 2007Applicant: International Business Machines CorporationInventors: MeiKei Ieong, Zhibin Ren, Haizhou Yin
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Publication number: 20060237791Abstract: A method of creating ultra thin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.Type: ApplicationFiled: June 23, 2006Publication date: October 26, 2006Applicant: International Business Machines CorporationInventors: Bruce Doris, Meikei Ieong, Zhibin Ren, Paul Solomon, Min Yang
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Patent number: 7091069Abstract: A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.Type: GrantFiled: June 30, 2004Date of Patent: August 15, 2006Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Meikei Ieong, Zhibin Ren, Paul M. Solomon, Min Yang
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Patent number: 7002214Abstract: A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.Type: GrantFiled: July 30, 2004Date of Patent: February 21, 2006Assignee: International Business Machines CorporationInventors: Diane C. Boyd, Judson R. Holt, MeiKei Ieong, Renee T. Mo, Zhibin Ren, Ghavam G. Shahidi
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Publication number: 20060022270Abstract: A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diane Boyd, Judson Holt, MeiKei Ieong, Renee Mo, Zhibin Ren, Ghavam Shahidi
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Publication number: 20060001095Abstract: A method of creating ultra tin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Doris, Meikei Ieong, Zhibin Ren, Paul Solomon, Min Yang
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Patent number: 5470877Abstract: A method of causing carcinoma regression is disclosed. One administers an effective amount of perillic acid methyl ester. The use of perillic acid methyl ester is disclosed. A pharmaceutical composition involving perillic acid methyl ester is disclosed.Type: GrantFiled: March 15, 1994Date of Patent: November 28, 1995Assignee: Wisconsin Alumni Research FoundationInventors: Michael N. Gould, Pamela L. Crowell, Charles E. Elson, Zhibin Ren