Abstract: A display substrate includes: a substrate and a plurality of subpixels arranged on the substrate, the plurality of subpixels are arranged in an array; the subpixel includes a subpixel driving circuit and a light emitting element, and the subpixel driving circuit includes a driving sub-circuit and a light emitting control sub-circuit coupled to each other; the light emitting element includes an anode pattern; the plurality of subpixels are divided into a plurality of groups of subpixels, each group of subpixels includes two subpixels arranged along a first direction, and two subpixel driving circuits included in the two subpixels share a same light emitting control sub-circuit, the light emitting control sub-circuit is configured to respectively control the driving sub-circuits in the two subpixels to write a driving signal to the anode pattern; the subpixel further includes a data line including a part extending along the first direction.

Abstract: A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.

Abstract: A display substrate includes an underlay substrate and a plurality of pixel unit groups. The plurality of pixel unit groups are located in a display region of the underlay substrate. At least one pixel unit group includes a plurality of sub-pixel groups, wherein at least one sub-pixel group includes a pixel circuit. The pixel circuit includes a first sub-pixel circuit, a second sub-pixel circuit, and a light emitting control sub-circuit. The first sub-pixel circuit and the second sub-pixel circuit are both electrically connected to the light emitting control sub-circuit. The light emitting control sub-circuit is configured to control a first light emitting element electrically connected to the first sub-pixel circuit to emit light, and to control a second light emitting element electrically connected to the second sub-pixel circuit to emit light.

Abstract: The present disclosure provides a display substrate and a display device, and belongs to the field of display technologies.

Abstract: In the technical field of display devices, there is a problem of low efficiency in image appearance inspection during the processing process of a display panel. In view of this, provided is an image acquisition system, comprising: a control device, an object loading device and an image acquisition apparatus. The control device is used for obtaining a target value of displacement between the object loading apparatus and the image acquisition apparatus according to an image signal, generating a control command, which carries the target displacement value, and then sending the control command to at least one of the object loading device and the image acquisition apparatus; and at least one of the object loading apparatus and the image acquisition apparatus moves according to the control command, until the definition of the image signal received by the control device in real time is greater than a preset definition threshold value.

Abstract: A shift register unit and a driving method thereof, a gate driving circuit, and a display device. The shift register unit includes: an input circuit, a first capacitor circuit, an output circuit, an output pull-down circuit, a coupling circuit, and an inverter circuit. The inverter circuit is coupled to an input control terminal, a first node, a second node, and a first level signal input terminal, and a second level signal input terminal; and used to control to connect or disconnect the second node and the first level signal input under the control of the input control terminal and the first level signal input terminal; also used to control to connect or disconnect the second node and the second level signal input terminal under the control of the first node and the second level signal input terminal.

Abstract: A display region includes a plurality of pixel driving circuitry setting regions arranged sequentially in a first direction, and each pixel driving circuitry setting region extends in a second direction intersecting the first direction. Each display circuitry includes a plurality of subpixels in one-to-one correspondence with the pixel driving circuitry setting regions, each subpixel includes a subpixel driving circuitry and a light-emitting element coupled to each other, the subpixel driving circuitry is located in a corresponding pixel driving circuitry setting region, the light-emitting element is located at a side of the subpixel driving circuitry away from the substrate, a width of the light-emitting element is greater than a width of the corresponding pixel driving circuitry setting region in the first direction, and a length of the light-emitting element is smaller than a length of the corresponding pixel driving circuitry setting region in the second direction.

Abstract: A display substrate, a display panel and a method of manufacturing a display substrate are provided. The display substrate includes: a substrate; a plurality of pixel units including at least a first pixel unit including a first light-emitting region and a first non-light-emitting region; a first light-emitting element arranged in the first light-emitting region, including a first electrode, a light-emitting layer and a second electrode; a scan driving circuit arranged in the first non-light-emitting region; and a first auxiliary electrode located in a first partial region in the first non-light-emitting region, wherein the scan driving circuit includes a plurality of scan driving sub-circuits located in a second partial region in the first non-light-emitting region; an orthographic projection of the first partial region on the substrate overlaps an orthographic projection of the second partial region on the substrate, and the first auxiliary electrode is electrically connected to the second electrode.

Abstract: Provided is a display substrate. The display substrate includes two pixels arranged along a first direction and adjacent to each other on a base substrate, and a pixel circuit in each of the two pixels includes a drive transistor, a first reset transistor, and a second reset transistor. A display device is also provided.

Abstract: Methods and systems are disclosed for managing performance states of a data fabric of a system on chip (SoC). Techniques disclosed include determining a performance state of the data fabric based on data fabric bandwidth utilizations of respective components of the SoC. A metric, characteristic of a workload centric to cores of the SoC, is derived from hardware counters, and, based on the metric, it is determined whether to alter the performance state.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: The present disclosure provides methods and compositions for diagnosis and for providing a prognosis of a cancer patient by assessing CK2 alpha 1 pseudogene (CSNK2A1P) status. The present disclosure also provides polypeptide, polynucleotide, host cell, and transgenic animal compositions associated with CSNK2A1P.

Abstract: This invention provides compositions and methods for the diagnosis and treatment of cancers that exhibit decreased SOCS-3 expression.

Abstract: The present disclosure provides methods and compositions for diagnosis and for providing a prognosis of a cancer patient by assessing CK2 alpha 1 pseudogene (CSNK2A1P) status. The present disclosure also provides polypeptide, polynucleotide, host cell, and transgenic animal compositions associated with CSNK2A1P.

Abstract: This invention provides compositions and methods for the diagnosis and treatment of cancers that exhibit decreased SOCS-3 expression.

Abstract: The present disclosure provides compositions, pharmaceutical preparations, kits and methods for inhibiting cell proliferation by contacting a cell expressing Fzd8 with a truncated Wnt2 polypeptide which acts as a dominant negative inhibitor of Fzd8 signaling. The present disclosure provides compositions, kits and methods for the detection of cancer by determining the level of Fzd8 and/or Wnt2 expression in a cell.