Abstract: The present disclosure provides an MABR-based method for treating rare earth mine tailwater, comprising: introducing rare earth mine tailwater into a sedimentation pond and simultaneously injecting pig farm breeding tailwater into the sedimentation pond, and fully mixing the two in the sedimentation pond for solid particulate sedimentation; performing pH adjustment, MABR enhancement treatment, percolation treatment with a percolation dam, and ecological purification with an ecological purification pond; and overflowing and discharging the rare earth mine tailwater purified by the ecological purification pond to a natural water body.

Abstract: Provided in the present application are a data processing method and apparatus based on data coding, and a device. The method comprises: performing N-channel error correction coding on data to be processed that is in information to be processed, so as to obtain N pieces of coded data to be processed; by using coded meta-channel data obtained by means of error correction coding, performing redundancy processing on the coded data to be processed, so as to obtain N pieces of response data; and then performing error correction decoding on the N pieces of response data, so as to obtain processing result information of the information to be processed.

Abstract: A method for parallel processing of retinal images includes: optimizing an objective function with a chaotic supply-demand algorithm to enhance a real retinal image; synthesizing a virtual retinal image by a hybrid image generation method; establishing a parallel multi-layer decomposed interval type-2 intuitionistic fuzzy convolutional neural network model based on the virtual retinal image and the enhanced real retinal image; and integrating outputs from a plurality of parallel multi-layer decomposed interval type-2 intuitionistic fuzzy convolutional neural network models as a final classification result.

Abstract: A method for parallel processing of retinal images includes: optimizing an objective function with a chaotic supply-demand algorithm to enhance a real retinal image; synthesizing a virtual retinal image by a hybrid image generation method; establishing a parallel multi-layer decomposed interval type-2 intuitionistic fuzzy convolutional neural network model based on the virtual retinal image and the enhanced real retinal image; and integrating outputs from a plurality of parallel multi-layer decomposed interval type-2 intuitionistic fuzzy convolutional neural network models as a final classification result.

Abstract: The present disclosure relates to a neural network artificial intelligence chip and a method for forming the same. The neural network artificial intelligence chip includes: a storage circuit, that includes a plurality of storage blocks; and a calculation circuit, that includes a plurality of logic units, the logic units being correspondingly coupled one-to-one to the storage blocks, and the logic unit being configured to acquire data in the corresponding storage block and store data to the corresponding storage block.

Abstract: The present invention relates to compounds according to Formula 1 and pharmaceutically acceptable salts, synthesis, intermediates, formulations, and methods of disease treatment therewith, including cancer, lymphocyte homing, chronic inflammation, neuropathic pain, fibrotic diseases, thrombosis, and cholestatic pruritus, mediated at least in part by ATX.

Abstract: The present invention relates to compounds according to Formula I and pharmaceutically acceptable salts, synthesis, intermediates, formulations, and methods of disease treatment therewith, including cancer, lymphocyte homing, chronic inflammation, neuropathic pain, fibrotic diseases, thrombosis, and cholestatic pruritus, mediated at least in part by ATX.

Abstract: The present invention relates to compounds according to Formula I and pharmaceutically acceptable salts, synthesis, intermediates, formulations, and methods of disease treatment therewith, including cancer, lymphocyte homing, chronic inflammation, neuropathic pain, fibrotic diseases, thrombosis, and cholestatic pruritus, mediated at least in part by ATX.

Abstract: The present invention relates to compounds according to Formula 1 and pharmaceutically acceptable salts, synthesis, intermediates, formulations, and methods of disease treatment therewith, including cancer, lymphocyte homing, chronic inflammation, neuropathic pain, fibrotic diseases, thrombosis, and cholestatic pruritus, mediated at least in part by ATX.

Abstract: The present invention relates to compounds according to Formula 1 and pharmaceutically acceptable salts, synthesis, intermediates, formulations, and methods of disease treatment therewith, including cancer, lymphocyte homing, chronic inflammation, neuropathic pain, fibrotic diseases, thrombosis, and cholestatic pruritus, mediated at least in part by ATX.

Abstract: An epitaxial growth method for preventing auto-doping effect is presented. This method starts with the removal of impurities from the semiconductor substrate and the reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region.

Abstract: The present disclosure discloses method and apparatus for image compression. The method includes: acquiring a threshold of a similarity score of an image; acquiring a first quality factor of the image, a first similarity score corresponding to the first quality factor, a second quality factor of the image, and a second similarity score corresponding to the second quality factor; obtaining a functional relationship between quality factor and similarity score of the image by means of curve fitting using the first quality factor, the first similarity score, the second quality factor, and the second similarity score; determining an optimum quality factor of the image according to the functional relationship between the quality factor and the similarity score and the threshold of the similarity score; and compressing the image according to the determined optimum quality factor. With the present disclosure, iterations in image compression can be completed in a very short time.

Abstract: The present disclosure discloses method and apparatus for image compression. The method includes: acquiring a threshold of a similarity score of an image; acquiring a first quality factor of the image, a first similarity score corresponding to the first quality factor, a second quality factor of the image, and a second similarity score corresponding to the second quality factor; obtaining a functional relationship between quality factor and similarity score of the image by means of curve fitting using the first quality factor, the first similarity score, the second quality factor, and the second similarity score; determining an optimum quality factor of the image according to the functional relationship between the quality factor and the similarity score and the threshold of the similarity score; and compressing the image according to the determined optimum quality factor. With the present disclosure, iterations in image compression can be completed in a very short time.

Abstract: The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches.

Abstract: The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.

Abstract: A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.

Abstract: A method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed. In addition to providing a good barrier to copper diffusion, good insulating properties, high etch selectivity with respect to dielectric insulators, boron carbide also provides good electrical characteristics because of its low dielectric constant of less than 5. The amorphous boron carbide is formed in a PECVD chamber by introducing a boron source gas such as B2H6, B5H9+, and carbon source gas such as CH4 and C2H6 at a deposition temperature of about 400° C. Any one, or any combination of the passivation, etch-stop, cap layers of the damascene structure can comprise boron carbide.