Abstract: The present application provides a double control gate semi-floating gate transistor and a method for preparing the same. A lightly doped well region provided with a U-shaped groove is located on a substrate; one part of a floating gate oxide layer covers sidewalls and a bottom of the U-shaped groove, the other part covers the lightly doped well region on one side, and the floating gate oxide layer covering the lightly doped well region; a floating gate polysilicon layer is filled in the U-shaped groove and covers the floating gate oxide layer; a polysilicon control gate stack includes a polysilicon control gate oxide layer on the floating gate polysilicon layer and a polysilicon control gate polysilicon layer on the polysilicon control gate oxide layer; a metal control gate stack includes a high-K dielectric layer and a metal gate.

Abstract: A multi-layer circuit board, successively constituted by surface sticking layer, single-layer circuit board, middle sticking layer, single-layer circuit board, surface sticking layer, said multi-layer circuit board is provided with a hole, a hole wall of said hole is formed with conductive seed layer, and partial outer surface of said surface sticking layer is formed with a circuit pattern layer of conductive seed layer, wherein said conductive seed layer comprises a ion implantation layer implanting below the hole wall of said hole and below partial outer surface of said surface sticking layer.

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Abstract: The present invention relates to a test system and method capable of simultaneously carrying out a high-throughput test of mechanical properties for miniature specimens. The system comprises one workstation (17) and a plurality of specimen test modules (16) installed horizontally or vertically on a workbench (15), wherein the workstation (17) comprises an operation interface, a data processing unit and a load output unit; each specimen test module (16) comprises a drive unit (5), an interchangeable clamp unit (8), a displacement sensor (2), and a load sensor (14); the workstation (17) controls the drive unit (5) of the specimen test module (16) and receives detection data of the displacement sensor (2) and the load sensor (14); each specimen test module (16) optionally performs mechanical property testing independently; and the workstation (17) controls simultaneously started testing of a plurality of specimens (9).

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Abstract: Disclosed is a pentamethine cyanine dye of formula (I) and a method of producing the same, where the dye is suitable as a fluorescent material for the STORM and SOFI super-resolution imaging.

Abstract: Disclosed is a method for manufacturing an LCP-based flexible copper-clad laminate, comprising: providing an LCP substrate and subjecting the LCP substrate to a Hall ion source pre-treatment; forming an ion-implanted layer in a certain depth range below the surface of the LCP substrate via ion implantation; performing plasma deposition to form a plasma deposition layer onto the ion-implanted layer; performing magnetron sputtering deposition to deposit copper ions onto the plasma deposition layer and form a magnetron sputtering deposition layer; and plating the magnetron sputtering deposition layer with a thickened copper layer to obtain the LCP-based flexible copper-clad laminate. Also disclosed is an LCP-based flexible copper-clad laminate, wherein a peeling strength between a copper foil and the LCP substrate of the LCP-based flexible copper-clad laminate is greater than or equal to 0.5 N/mm, a surface roughness between the two is smaller than or equal to 0.

Abstract: Disclosed are a fluorescent dye, a preparation method and an application thereof. The fluorescent dye has a structure of formula (I), where X and Y are independently selected from O, S, C(CH3)2 and NR6; R2 and R3 are independently hydrogen or a functional group; R1, R4, R5 and R6 are independently selected from functional groups; and Z? is a negative ion. The fluorescent dye has an ability to permeate the living cell membrane, so that it can be used in the fluorescence imaging of living cell microstructures, and can also be used in the STED super-resolution fluorescence imaging and laser scanning confocal microscopy of live cells.

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Abstract: The present invention relates to a test system and method capable of simultaneously carrying out a high-throughput test of mechanical properties for miniature specimens. The system comprises one workstation (17) and a plurality of specimen test modules (16) installed horizontally or vertically on a workbench (15), wherein the workstation (17) comprises an operation interface, a data processing unit and a load output unit; each specimen test module (16) comprises a drive unit (5), an interchangeable to clamp unit (8), a displacement sensor (2), and a load sensor (14); the workstation (17) controls the drive unit (5) of the specimen test module (16) and receives detection data of the displacement sensor (2) and the load sensor (14); each specimen test module (16) optionally performs mechanical property testing independently; and the workstation (17) is controls simultaneously started testing of a plurality of specimens (9).

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Abstract: Disclosed are a fluorescent dye, a preparation method and an application thereof. The fluorescent dye has a structure of formula (I), where X and Y are independently selected from O, S, C(CH3)2 and NR6; R2 and R3 are independently hydrogen or a functional group: R1, R4, R5 and R6 are independently selected from functional groups; and Z? is a negative ion. The fluorescent dye has an ability to permeate the living cell membrane, so that it can be used in the fluorescence imaging of living cell microstructures, and can also be used in the STED super-resolution fluorescence imaging and laser scanning confocal microscopy of live cells.

Abstract: Disclosed is a pentamethine cyanine dye of formula (I) and a method of producing the same, where the dye is suitable as a fluorescent material for the STORM and SOFI super-resolution imaging.

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and/or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.