Patents by Inventor Zhijian J. Yang
Zhijian J. Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9166588Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.Type: GrantFiled: January 20, 2014Date of Patent: October 20, 2015Assignee: GLOBALFOUNDIRES INC.Inventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian J. Yang
-
Publication number: 20150207505Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and a well formed in the semiconductor substrate. The well includes a first region having a first concentration of ions, and at least one second region having a second concentration that is less than the first concentration. First and second FETs are formed on the well. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.Type: ApplicationFiled: January 20, 2014Publication date: July 23, 2015Applicant: International Business Machines CorporationInventors: Kai D. Feng, Wai-Kin Li, Ping-Chuan Wang, Zhijian J. Yang
-
Patent number: 8759175Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.Type: GrantFiled: March 26, 2012Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
-
Patent number: 8687445Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: GrantFiled: March 18, 2013Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
-
Patent number: 8422322Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: GrantFiled: November 3, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
-
Publication number: 20120184076Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
-
Patent number: 8193575Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.Type: GrantFiled: February 7, 2008Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
-
Publication number: 20120051166Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: ApplicationFiled: November 3, 2011Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
-
Patent number: 8098536Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: GrantFiled: January 24, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
-
Patent number: 7904273Abstract: A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.Type: GrantFiled: February 16, 2009Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Qizhi Liu, Ping-Chuan Wang, Kimball M. Watson, Zhijian J. Yang
-
Publication number: 20100210043Abstract: A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.Type: ApplicationFiled: February 16, 2009Publication date: August 19, 2010Applicant: International Business Machines CorporationInventors: Qizhi Liu, Ping-Chuan Wang, Kimball M. Watson, Zhijian J. Yang
-
Patent number: 7723824Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V).Type: GrantFiled: May 4, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Fernando Guarin, J. Edwin Hostetter, Jr., Stewart E. Rauch, III, Ping-Chuan Wang, Zhijian J. Yang
-
Patent number: 7675378Abstract: Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range.Type: GrantFiled: May 2, 2008Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Kai D. Feng, Kafai Lai, Ping-Chuan Wang, Zhijian J. Yang
-
Patent number: 7609121Abstract: Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range.Type: GrantFiled: March 28, 2008Date of Patent: October 27, 2009Assignee: International Business Machines CorporationInventors: Kai D. Feng, Kafai Lai, Ping-Chuan Wang, Zhijian J. Yang
-
Publication number: 20090243739Abstract: Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range.Type: ApplicationFiled: May 2, 2008Publication date: October 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Kafai Lai, Ping-Chuan Wang, Zhijian J. Yang
-
Publication number: 20090243738Abstract: Disclosed are embodiments of a voltage controlled oscillator (VCO) capable of non-volatile self-correction to compensate for process variations and to ensure that the center frequency of the oscillator is maintained within a predetermined frequency range. This VCO incorporates a pair of varactors connected in parallel to an inductor-capacitor (LC) tank circuit for outputting a periodic signal having a frequency that is proportional to an input voltage. A control loop uses a programmable variable resistance e-fuse to set a compensation voltage to be applied to the pair of varactors. By adjusting the compensation voltage, the capacitance of the pair of varactors can be adjusted in order to selectively increase or decrease the frequency of the periodic signal in response to a set input voltage and, thereby to bring the frequency of that periodic signal into the predetermined frequency range.Type: ApplicationFiled: March 28, 2008Publication date: October 1, 2009Inventors: Kai D. Feng, Kafai Lai, Ping-Chuan Wang, Zhijian J. Yang
-
Publication number: 20090200598Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.Type: ApplicationFiled: February 7, 2008Publication date: August 13, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
-
Publication number: 20090190413Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.Type: ApplicationFiled: January 24, 2008Publication date: July 30, 2009Inventors: Louis L. C. Hsu, Rajiv V. Joshi, Zhijian J. Yang, Ping-Chuan Wang
-
Patent number: 7238565Abstract: A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (V?CB of less than 1 V).Type: GrantFiled: December 8, 2004Date of Patent: July 3, 2007Assignee: International Business Machines CorporationInventors: Fernando Guarin, J. Edwin Hostetter, Jr., Stewart E. Rauch, III, Ping-Chuan Wang, Zhijian J. Yang