Patents by Inventor Zhijiong Luo
Zhijiong Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10096717Abstract: The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.Type: GrantFiled: November 18, 2011Date of Patent: October 9, 2018Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Huilong Zhu, Qingqing Liang, Haizhou Yin, Zhijiong Luo
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Patent number: 9997640Abstract: Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.Type: GrantFiled: August 31, 2016Date of Patent: June 12, 2018Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Zhijiong Luo
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Publication number: 20180121212Abstract: Memory structures are provided, where a fast SRAM in an mNVSRAM block may serve as the buffer for a large block NVM memory to increase the data exchange rate between computing units or processor cores and the large NVM memory. The mNVSRAM blocks may also provide a fast boot function, where a boot code may be stored in the NVM parts of the mNVSRAM block, and due to the high bandwidth communication between fast SRAM part and the associated NVM memories, the boot code may be transferred into the fast SRAM in one or a few clock cycles enabling fast boot up function. Similarly, code stored in the NVM parts of an mNVSRAM block may be transferred into fast SRAM rapidly at wake-up time enabling fast wake up and voiding a need to wake up any other memory part, which may also result in energy savings for the computing system.Type: ApplicationFiled: December 27, 2017Publication date: May 3, 2018Applicant: Aspiring Sky Co. LimitedInventors: Zhijiong LUO, Xiaoming Jin, Shu Wang, Zuqu Li
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Publication number: 20180113812Abstract: Technologies for re-configurable non-volatile memory structures and systems for FPGA, as well as, non-volatile static random access memory (nvSRAM) cells with multiple a non-volatile memory (NVM) bits. Proposed structures may quickly switch/reconfigure look-up tables (LUTs) and/or reconfigure FPGA routings. Memory structures according to some embodiments may reduce the switching/reconfiguring times to one or a few clock cycles. Thus, fast or real time FPGA reconfiguration is enabled, one LUT may serve multiple functions, thereby, a fraction of current FPGAs may be used to perform multi-functions, which may substantially reduce FPGA chip areas. Structures according to embodiments may further provide simple routing for entire system by re-configuration and enhanced data security by avoiding external data transmission.Type: ApplicationFiled: October 18, 2017Publication date: April 26, 2018Applicant: Aspiring Sky Co., LimitedInventors: Zhijiong Luo, Xiaoming Jin, Shu Wang
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Publication number: 20180081802Abstract: Technologies are generally described herein for a hybrid non-volatile memory structure that includes a number of SRAM buffers. SRAM access times may be achieved for non-volatile read/write operations by performing access queue buffered read/write operations first. The SRAM buffer may be shareable as a system SRAM. In other examples, a hybrid non-volatile memory according to some embodiments may include a high speed block and a high endurance block to store different types of data with different access needs. The hybrid non-volatile memory may also include a normal block to store the data which is non-frequently changed.Type: ApplicationFiled: September 14, 2017Publication date: March 22, 2018Applicant: Aspiring Sky Co., LimitedInventors: Zhijiong LUO, Shu WANG, Xiaoming JIN
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Publication number: 20180082732Abstract: Technologies are generally described herein for static random access memory (SRAM) based memory structures and methods thereof such as multi-bit non-volatile static random-access memory (nvSRAM) with arrayed SRAM and NVM or SRAM buffered one time programmable (OTP) memories, RRAMs or other resistive RAMs.Type: ApplicationFiled: September 14, 2017Publication date: March 22, 2018Applicant: Aspiring Sky Co., LimitedInventors: Zhijiong LUO, Xiaoming JIN, Shu WANG
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Patent number: 9853153Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.Type: GrantFiled: November 27, 2012Date of Patent: December 26, 2017Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin, Qingqing Liang
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Patent number: 9812428Abstract: Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.Type: GrantFiled: October 21, 2016Date of Patent: November 7, 2017Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Zhijiong Luo
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Patent number: 9716175Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.Type: GrantFiled: November 27, 2012Date of Patent: July 25, 2017Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Huilong Zhu, Qingqing Liang, Haizhou Yin, Zhijiong Luo
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Patent number: 9691899Abstract: A semiconductor structure is provided, comprising a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located above the base region (100), and the base region (100) is supported above the substrate (130) by the support structure (131), wherein the support structure (131) has a sigma-shaped lateral cross-section; an isolation structure (123) is formed below edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and a source/drain region is formed on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also provided.Type: GrantFiled: November 27, 2012Date of Patent: June 27, 2017Inventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
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Patent number: 9583622Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench.Type: GrantFiled: July 6, 2012Date of Patent: February 28, 2017Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin, Qingqing Liang
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Publication number: 20170040295Abstract: Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.Type: ApplicationFiled: October 21, 2016Publication date: February 9, 2017Applicant: Empire Technology Development LLCInventor: Zhijiong Luo
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Patent number: 9548317Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure.Type: GrantFiled: May 22, 2012Date of Patent: January 17, 2017Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
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Patent number: 9542990Abstract: A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor which includes: an oxide substrate; an oxide film on the oxide substrate, wherein an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxide film and electrically connected with the interfacial layer; a front gate on the oxide film; and a back gate on a lower surface of the oxide substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation.Type: GrantFiled: February 28, 2012Date of Patent: January 10, 2017Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Zhengyong Zhu, Zhijiong Luo
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Patent number: 9543188Abstract: The present invention provides an isolation structure for a semiconductor substrate and a method for manufacturing the same, as well as a semiconductor device having the structure. The present invention relates to the field of semiconductor manufacture. The isolation structure comprises: a trench embedded in a semiconductor substrate; an oxide layer covering the bottom and sidewalls of the trench, and isolation material in the trench and on the oxide layer, wherein a portion of the oxide layer on an upper portion of the sidewalls of the trench comprises lanthanum-rich oxide. By the trench isolation structure according to the present invention, metal lanthanum in the lanthanum-rich oxide can diffuse into corners of the oxide layer of the gate stack, thus alleviating the impact of the narrow channel effect and making the threshold voltage adjustable.Type: GrantFiled: March 2, 2011Date of Patent: January 10, 2017Assignee: INSTITUTE OF MICROELECTONICS, CHINESE ACADEMY OF SCIENCESInventors: Zhijiong Luo, Haizhou Yin, Huilong Zhu, Huicai Zhong
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Publication number: 20160372602Abstract: Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.Type: ApplicationFiled: August 31, 2016Publication date: December 22, 2016Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Zhijiong Luo
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Patent number: 9508685Abstract: Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.Type: GrantFiled: July 29, 2014Date of Patent: November 29, 2016Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Zhijiong Luo
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Publication number: 20160343896Abstract: A solar cell structure is disclosed, which includes a solar cell array, including multiple solar cells arranged in parallel, wherein each solar cell includes a first semiconductor layer, a second semiconductor layer under the first semiconductor layer, top electrodes and bottom electrodes formed on surfaces of the first and second semiconductor layers, respectively; a top wire group on top of the solar cell array wherein each wire connects each of the multiple solar cells; a bottom wire group under the solar cell array wherein each wire connects each of the multiple solar cells and is placed away from the wires of the top wire group; and conductive adhesive on top of the top electrodes and on top of the bottom electrodes, being sandwiched between the top wire group and the solar cell array as well as between the bottom wire group and the solar cell array.Type: ApplicationFiled: August 2, 2016Publication date: November 24, 2016Inventors: Haizhou YIN, Huilong ZHU, Zhijiong LUO
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Patent number: 9496178Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer; a first fin being formed by patterning the semiconductor layer; and a second fin being formed by patterning the semiconductor layer, wherein: top sides of the first and second fins have the same height; bottom sides of the first and second fins adjoin the semiconductor layer; and the second fin is higher than the first fin. According to the present disclosure, a plurality of semiconductor devices with different dimensions can be integrated on the same wafer. As a result, manufacturing process can be shortened and manufacturing cost can be reduced. Furthermore, devices with different driving capabilities can be provided.Type: GrantFiled: November 18, 2011Date of Patent: November 15, 2016Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
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Patent number: 9484328Abstract: Technologies are generally described related to electrical connectivity and heat mitigation in three dimensional integrated circuit (IC) integration through backside through silicon vias (TSVs) and micro-channels. In some examples, micro-channels may be formed in a wafer using a reactive ion etching (RIE) or similar fabrication process. Upon alignment and bonding of two wafers, selected micro-channels may be converted into TSVs by a further RIE or similar process and filled.Type: GrantFiled: August 1, 2014Date of Patent: November 1, 2016Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Zhijiong Luo