Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, core regions, isolation regions, a layer stack, channel structures, and an isolation structure. Each core region is surrounded by one or more of the isolation regions. The layer stack is formed in each core region and includes first dielectric layers and conductor layers that are alternatingly stacked over each other. The channel structures are formed through the layer stack. The isolation structure is formed in one or more of the isolation regions, and includes second dielectric layers and third dielectric layers that are alternatingly stacked over each other.

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device comprises: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers and comprising a conductive layer sandwiched between two dielectric layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer.

Abstract: The present disclosure provides a three-dimensional memory comprising: a storage channel structure vertically penetrating a plurality of stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising: a block layer in contact with the select gate structure, an insulating layer covering the block layer, and a second channel layer in contact with the insulating layer and the first channel layer.

Abstract: The present disclosure provides a three-dimensional memory device and a manufacturing method thereof, the three-dimensional memory device including: a plurality of stacked layers; a storage channel structure vertically penetrating the stacked layers and comprising a first channel layer; a select gate structure on the plurality of stacked layers; and a select channel structure vertically penetrating the select gate structure and comprising a second channel layer; wherein an outer sidewall of the second channel layer is in contact with an inner sidewall of the first channel layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a first stop layer on the sacrificial layer, an N-type doped semiconductor layer on the first stop layer, and a dielectric stack on the N-type doped semiconductor layer are sequentially formed. A plurality of channel structures each extending vertically through the dielectric stack and the N-type doped semiconductor layer are formed, stopping at the first stop layer. The dielectric stack is replaced with a memory stack, such that each of the plurality of channel structures extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate, the sacrificial layer, and the first stop layer are sequentially removed to expose an end of each of the plurality of channel structures. A conductive layer is formed in contact with the ends of the plurality of channel structures.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.

Abstract: A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region and word line pick-up structures in a first portion of a second region. The first region and the second region are arranged in a first direction. The 3D memory device also includes word lines each extending in the first region and a second portion of the second region. The first portion and the second portion of the second region are arranged in a second direction perpendicular to the first direction. The 3D memory device also includes dummy channel structures in the second portion of the second region. Adjacent channel structures are spaced apart from each other by a first distance. Adjacent dummy channel structures are spaced apart from each other by a second distance that is smaller than the first distance.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, and a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a first width of the semiconductor channel at the bottom portion of the channel structure below the angled structure is smaller than a second width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure of alternating insulating layers and word line layers, a first top select gate (TSG) layer over the stack structure, and a separation structure extending through the first TSG layer, where the first TSG layer is divided by the separation structure into a first sub TSG layer and a second sub TSG layer. The semiconductor device includes a conductive layer positioned between the first sub TSG layer and the separation structure, and between the second sub TSG layer and the separation structure.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.