Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.

Abstract: A method for manufacturing a nanosheet semiconductor device includes: forming a liner layer to cover first and second fin structures, each of the fin structures including a stacked structure, a poly gate disposed on the stacked structure, and inner spacers, the stacked structure including sacrificial features covered by the inner spacers, and channel features disposed to alternate with the sacrificial features; forming a dielectric layer to cover the liner layer, the dielectric layer including an upper portion, a lower portion, and an interconnecting portion that interconnects the upper and lower portions and that laterally covers the liner layer; subjecting the upper and lower portions to a directional treatment; and removing the upper and interconnecting portions of the dielectric layer and a portion of the liner layer, to form a liner and a bottom dielectric insulator disposed on the liner.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.

Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.

Abstract: Apparatus and methods are provided for integrally packaging antenna devices with semiconductor IC (integrated circuit) chips, wherein IC chips are packaged with dielectric resonators antennas that are integrally constructed as part of a package molding (encapsulation) process, for example, to form compact integrated radio/wireless communications systems for millimeter wave applications.

Abstract: Low-profile, compact embedded antenna designs are provided for use with computing devices, such as laptop computers, which enable ease of integration within computing devices with limited space, while providing suitable antenna characteristics (e.g., impedance matching and radiation efficiency) over a desired bandwidth of operation. Compact antenna designs with reduced antenna size (e.g., antenna height) and increased operational bandwidth (e.g., broadband impedance matching) are achieved using slotted ground plane designs and/or doubling antenna feeding schemes.

Abstract: A compact sized embedded, multiband, multi-standard, interoperable antenna for portable devices used in wireless applications is provided. The antenna design includes an asymmetrical structure provided on a double-sided printed circuit board. The asymmetrical structure covers both the ultra-wideband and the wireless local area network band. The asymmetrical structure provided on the front side of the printed circuit board is a primary radiator with a supplement strip radiator, whereby the bottom of the primary radiator is close to the vertical ground plane and fed by a probe extended from a coaxial line. The asymmetrical structure on the front side provides a well-matched bandwidth covering the ultra-wideband band of 3.1 GHz to 10.6 GHz. A second supplement strip is provided on the backside of the printed circuit board which provides the second resonance at the 2.4 GHz wireless local area network band.

Abstract: Low-profile, compact UWB embedded antenna designs are provided for use with computing devices, such as laptop computers, which enable ease of integration within computing devices with limited space, while providing suitable antenna characteristics (e.g., impedance matching and radiation efficiency) over an operating bandwidth of about 1 GHz to about 11 GHz.

Abstract: A suspended plate antenna for broadband applications is disclosed. The antenna comprises a plate radiator, a slot cut in the plate radiator, and a substantially balanced feeding structure symmetrically feeding the plate radiator with respect to at least one midline of the plate radiator.

Abstract: Feeding structures for suspended plate antennas are disclosed hereinafter for enhancing the impedance bandwidth performance thereof. In any of these feeding structures, a multi-dimensional broadband impedance transformer is integrated with a suspended plate antenna. The impedance transformer electrically connects the radiating plate and feeding probe of the suspended plate antenna. As a result, the impedance bandwidth is increased. Moreover, the multi-dimensional design of the impedance transformer is variable to allow the flexible design and adjustment of the feeding structure.

Abstract: A suspended plate antenna for broadband applications is disclosed. The antenna comprises a plate radiator, a slot cut in the plate radiator, and a substantially balanced feeding structure symmetrically feeding the plate radiator with respect to at least one midline of the plate radiator.

Abstract: Feeding structures for suspended plate antennas are disclosed hereinafter for enhancing the impedance bandwidth performance thereof. In any of these feeding structures, a multi-dimensional broadband impedance transformer is integrated with a suspended plate antenna. The impedance transformer electrically connects the radiating plate and feeding probe of the suspended plate antenna. As a result, the impedance bandwidth is increased. Moreover, the multi-dimensional design of the impedance transformer is variable to allow the flexible design and adjustment of the feeding structure.

Abstract: A broadband plate antenna (402) is disclosed, which includes a ground conductor (407) and a radiating element (406) which is separated from the ground conductor (407). The antenna also includes an impedance matching stub (404) electrically coupled to the radiating element (406), and means for feeding the radiating element (406), wherein the means for feeding includes a feed point (410) disposed on the impedance matching stub (404).