Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads and the scribe line regions; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. The second dike structures are arranged corresponding to the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures and the first dike structures.

Abstract: A wafer level packaging structure for image sensors and a wafer level packaging method for image sensors are provided. The wafer level packaging structure includes: a wafer to be packaged including multiple chip regions and scribe line regions between the chip regions; pads and image sensing regions located on a first surface of the wafer and located in the chip regions; first dike structures covering surfaces of the pads; a packaging cover arranged facing the first surface of the wafer; and second dike structures located on a surface of the packaging cover. Projections of the second dike structures onto the first surface of the wafer are included in the scribe line regions. The packaging cover and the wafer are jointed fixedly via the second dike structures, while tops of the first dike structures and the surface of the packaging cover are contacted.

Abstract: This invention relates to an amplifier device and a predistortion control method. The amplifier device comprises a predistortion unit, a predistortion control unit, and an amplifier unit, of which the predistortion control unit controls the predistortion unit in accordance with a signal fed back from the amplifier unit. The predistortion control method comprises determining power of a left side lobe of two side lobes of a frequency spectrum of the signal fed back from the amplifier unit; determining power of a right side lobe of two side lobes of a frequency spectrum of the signal fed back from the amplifier unit; determining a cost function in accordance with the power of the first and right side lobes, and controlling the predistortion unit in accordance with the cost function.

Abstract: An adaptive digital predistortion device and method, the adaptive digital predistortion device including a predistortion unit for predistorting an input signal according to a predistortion parameter stored in a look-up table; a cost function generation unit for generating a cost function; a fixed segment point determination unit for determining a fixed segment point; and an update unit for updating parameters (u1, u2, ka) according to the cost function to update the look-up table based on the updated parameters (u1, u2, ka), wherein ka is an updated adaptive segment point, u1 and u2 are slopes on two sides of the adaptive segment point ka; and for subsequently updating parameters (v1, v2) according to the cost function to update the look-up table based on the updated parameters (v1, v2) and the fixed segment point, wherein v1 and v2 are slopes on two sides of the fixed segment point.

Abstract: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.

Abstract: The present invention relates to an adaptive digital predistortion device and method. The adaptive digital predistortion device comprising: a predistortion unit for predistorting an input signal according to a predistortion parameter stored in a look-up table; a cost function generation unit for generating a cost function; a fixed segment point determination unit for determining a fixed segment point; and an update unit for updating parameters (u1, u2, ka) according to the cost function to update the look-up table based on the updated parameters (u1, u2, ka), wherein ka is an updated adaptive segment point, u1 and u2 are slopes on two sides of the adaptive segment point ka; and for subsequently updating parameters (v1, v2) according to the cost function to update the look-up table based on the updated parameters (v1, v2) and the fixed segment point, wherein v1 and v2 are slopes on two sides of the fixed segment point.

Abstract: This invention relates to an amplifier device and a predistortion control method. The amplifier device comprises a predistortion unit, a predistortion control unit, and an amplifier unit, of which the predistortion control unit controls the predistortion unit in accordance with a signal fed back from the amplifier unit. The predistortion control method comprises determining power of a left side lobe of two side lobes of a frequency spectrum of the signal fed back from the amplifier unit; determining power of a right side lobe of two side lobes of a frequency spectrum of the signal fed back from the amplifier unit; determining a cost function in accordance with the power of the first and right side lobes, and controlling the predistortion unit in accordance with the cost function.

Abstract: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Abstract: The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured.

Abstract: The present invention relates to an optical converter and a manufacturing method thereof and a light emitting diode. An optical converter for a light emitting diode includes two substrates, in which, a annular first cavity wall is arranged between the two substrates, and an airtight space filled with an optical conversion substance is surrounded by the first cavity wall and the two substrates. The invention implements the encapsulation and manufacturing of the optical conversion substance for the LED. The structure and the manufacturing method according to the invention can be utilized to encapsulate an active optical conversion substance in the optical converter while avoiding the active optical conversion substance reacting to other active substance, e.g., oxygen, during manufacturing. Furthermore, the optical conversion substance is encapsulated with wafer level chip size packaging to thereby improve the efficiency of manufacturing the optical converter and reduce the cost.

Abstract: The invention discloses a packaging structure and packaging method. The packaging structure includes a solder bump, a pad located on a front side of a chip, and an intermediate metal layer which connects the solder bump and the pad, wherein a through hole passing from a back side of the chip to the pad is provided on the chip, and the intermediate metal layer is connected to the pad within the through hole. In the packaging structure, a through hole is formed on the back side of the chip to expose the pad on the front side of the chip and the intermediate metal layer is connected to the pad within the through hole. This provides a relatively large contacting area therebetween. The connection thus formed is more reliable and stable, compared with the prior art structure.

Abstract: The application provides a packaging structure, a packaging method and a photosensitive device. The packaging structure includes a substrate structure, a chip and a solder bump electrically connecting with a pad on the chip. The solder bump is located on the substrate structure, so that the multilayer coverage structure required when forming a bump on a side of the chip in the prior art packaging structure is avoided. In this way, the thickness of the packaging structure is reduced and the reliably of the packaging structure is improved.

Abstract: The present invention provides a packaging structure and a method for fabricating the same, the packaging structure includes a chip, a compatible pad provided on the chip, an intermediate metal layer electrically connecting with the compatible pad, a solder bump, and a redistribution metal layer electrically connecting with the solder bump, wherein the redistribution metal layer connects with the intermediate metal layer directly to form an electrical connection. Also, some connections between the redistribution metal layer and the intermediate metal layer are in a manner of concave shape, while other connections between the redistribution metal layer and the intermediate metal layer are in a manner of “-” shape, so that the number of the connections increases while the stability of connection is ensured.

Abstract: The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Abstract: A quick installing axial deformation transducer has diametrically opposite strain gages to measure the axial deformation or load on a uniform or tapered cross-section member. The strain gages are four in number with two on each diametrically side of the member. Adjacent strain gages are orientated and electrically connected on adjacent arms of a bridge to measure axial deformation and to cancel outputs caused by bending or torsional moments as a result of the axial force applied.