Abstract: A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.

Abstract: A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.

Abstract: A memory array can be optimized for SPICE simulation by modeling the memory array as a collection of boundary elements that track the cell states of memory cells connected to a particular array terminal. By maintaining a cell state distribution for each boundary element, the simulation behavior at the array terminal associated with that boundary element can be accurately determined by modeling each unique cell state, multiplying the results by the corresponding quantities from the cell state distribution, and then adding the results to obtain final values for the array terminal. This allows accurate simulation results to be achieved without needing to simulate each cell independently. Furthermore, by removing any references to unoccupied cell states (e.g., by removing such states from the cell state distribution and/or eliminating model equations for such states), the memory and cpu usage requirements during the simulation can be minimized.

Abstract: A memory array can be optimized for SPICE simulation by modeling the memory array as a collection of boundary elements that track the cell states of memory cells connected to a particular array terminal. By maintaining a cell state distribution for each boundary element, the simulation behavior at the array terminal associated with that boundary element can be accurately determined by modeling each unique cell state, multiplying the results by the corresponding quantities from the cell state distribution, and then adding the results to obtain final values for the array terminal. This allows accurate simulation results to be achieved without needing to simulate each cell independently. Furthermore, by removing any references to unoccupied cell states (e.g., by removing such states from the cell state distribution and/or eliminating model equations for such states), the memory and cpu usage requirements during the simulation can be minimized.