Abstract: Disclosed is a space partitioning method for a database table, including: determining a first data amount within a first time period and a second data amount within a second time period of the database table; calling a target network model, inputting the first data amount and the second data amount into the target network model, and outputting a third data amount within the target time period, wherein the target network model is configured to predict a data amount of a next time period based on data amounts of a previous time period and a current time period; and determining a number of target regions based on the third data amount within the target time period, and partitioning, based on the number of target regions, a space in the database table configured to store the data to be stored.

Abstract: Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started.

Abstract: The present disclosure provides a method for conformal array pattern synthesis based on a solution space pruning particle swarm optimization algorithm (PSO), the method comprises taking a suppression index of a peak side lobe level (SLL) as a first index, obtaining the first array element excitation satisfying the first index under the constraint of the dynamic range ratio (DRR) of the array element excitation amplitude through iterations; obtaining a second array element excitation satisfying the multiple optimization objectives under the constraint of the DRR of the array element excitation amplitude by a solution algorithm according to the first array element excitation.

Abstract: Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.

Abstract: Disclosed is a multitarget constant false alarm rate detection method based on the signal proxy, which belongs to the technical field of radar constant false alarm rate detection. The method realizes target detection by utilizing the correlation between linear measurements of the radar intermediate frequency signal and the sensing matrix. To achieve a desired false alarm rate, the method determines the threshold by estimating the distributed parameters of the reduced sample set obtained by removing the detected targets from the original sample set. The method provided by the present disclosure can adapt to the sparsity of the signals, realize target detection without relying on the pre-estimated environmental background level, and effectively mitigate the multitarget shadowing effect.

Abstract: Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started. (FIG.

Abstract: An inductor current reconstruction circuit of a power converter can include: a switching current sampling circuit configured to acquire at least one of a current flowing through a main power transistor and a current flowing through a rectifier transistor to generate a switching current sampling signal; an inductor current generating circuit configured to generate a reconstruction signal representing an inductor current in one complete switching cycle; and where the reconstruction signal comprises the switching current sampling signal and a current analog signal generated according to the switching current sampling signal and an inductor voltage signal representing a voltage across an inductor in the power converter.

Abstract: Disclosed is a method for direction-of-arrival estimation based on sparse reconstruction in the presence of gain-phase error, which comprises the following steps: firstly, estimating a noise power and an gain error from an array received signal by adopting a characteristic decomposition method; then, based on a compensated covariance matrix, transforming a direction-of-arrival estimation problem into a non-convex optimization problem in a sparse frame by a method of sparse reconstruction; finally, estimating a grid angle and a deviation angle by using an alternate optimization method. This estimation method can effectively eliminate the influence of a phase error in direction-of-arrival estimation, and has better adaptability, which improves the resolution and estimation accuracy of the algorithm.

Abstract: The present disclosure provides a method for conformal array pattern synthesis based on a solution space pruning particle swarm optimization algorithm (PSO), the method comprises taking a suppression index of a peak side lobe level (SLL) as a first index, obtaining the first array element excitation satisfying the first index under the constraint of the dynamic range ratio (DRR) of the array element excitation amplitude through iterations; obtaining a second array element excitation satisfying the multiple optimization objectives under the constraint of the DRR of the array element excitation amplitude by a solution algorithm according to the first array element excitation.

Abstract: The present disclosure provides a method for predicting co-channel interference (CCI) of a satellite-to-ground downlink under a low-orbit satellite constellation. The method includes: obtaining CCI values in a first time period and CCI values in a second time period; constructing a CCI model based on the CCI values in the first time period and a dropout wavelet neural network (WNN); updating parameters of the CCI model; inputting the CCI values in the second time period into an updated CCI model to obtain accuracy; determining whether the accuracy is greater than an accuracy threshold; and if the accuracy is greater than the accuracy threshold, reconstructing the CCI model; or if the accuracy is less than or equal to the accuracy threshold, outputting the updated CCI model; and predicting CCI values of each link at a next moment based on the updated CCI model.

Abstract: A semiconductor wafer is inspected using a main laser beam and a secondary laser beam. The secondary laser beam leads the main laser beam and has lower power than the main laser beam. Using the secondary laser beam, a particle is detected on the semiconductor wafer having a size that satisfies a threshold. In response to detecting the particle, the power of the main laser beam and the power of the secondary laser beam are reduced. The particle passes through the main laser beam with the main laser beam at reduced power. After the particle has passed through the main laser beam with the main laser beam at the reduced power, the power of the main laser beam and the power of the secondary laser beam are restored in a controlled manner that is slower than a single step.

Abstract: A driving circuit and a driving method are provided. The driving circuit includes a power stage circuit and a full-bridge circuit. The power stage circuit is configured to receive an input voltage, and generate an output voltage at an output port of the power stage circuit. The full-bridge circuit is coupled to the output port of the power stage circuit and is configured to perform charging and discharging on a piezoelectric load. An operating mode of the full-bridge circuit is controlled, so that a supply voltage signal for driving the piezoelectric load during a first operating interval of an operating cycle corresponds to a reference voltage in a first interval, and the supply voltage signal during a second operating interval of the operating cycle corresponds to the reference voltage in a second interval. The driving circuit has a small volume, which is conducive to circuit integration.

Abstract: The present disclosure discloses an on-chip synchronous self-repairing system based on a low-frequency reference signal. The system adopts a dual-input PLL stellate coupled structure or a dual-input PLL butterfly-shaped coupled structure, and delay of the whole loop is made to be an integral multiple of the reference signal by synchronizing the transmitted reference signal with the received reference signal, so as to ensure synchronization of local oscillation signal of each IC chip. The transmission wire based on an adjustable left-handed material is used as a delay wire to connect the dual-input PLL, thereby achieving low loss and reducing the physical distance of the delay wire. The system has the advantages of small area, low loss, strong adaptability and strict synchronization in various environments.

Abstract: Disclosed is a zero-delay phase-locked loop frequency synthesizer based on multi-stage synchronization, which belongs to the technical field of integrated circuits. The zero-delay phase-locked loop frequency synthesizer comprises: a phase frequency detector, a charge pump, a loop pass filter, a voltage control oscillator and a multi-stage synchronization divider, wherein the phase frequency detector, the charge pump, the loop pass filter and the voltage control oscillator are connected in sequence; an output OUT of the voltage control oscillator is connected to an input IN of the multi-stage synchronization divider; and an output OUT of the multi-stage synchronization divider is connected to an input IN of the phase frequency detector, so as to form a feedback path.

Abstract: A driving circuit for driving a piezoelectric load, can include: an energy-storage capacitor; a first power stage circuit configured to convert an input voltage into a first voltage, and to store the first voltage in the energy-storage capacitor; a second power stage circuit configured to receive the first voltage to charge the piezoelectric load during a first operation interval of an operation period, such that a power supply voltage signal provided to the piezoelectric load in the first operation interval corresponds to a reference voltage in a first interval; and a discharging circuit configured to discharge the piezoelectric load during a second operation interval of the operation period, such that the power supply voltage signal in the second operation interval corresponds to the reference voltage in a second interval.

Abstract: Disclosed is a space partitioning method for a database table, including: determining a first data amount within a first time period and a second data amount within a second time period of the database table; calling a target network model, inputting the first data amount and the second data amount into the target network model, and outputting a third data amount within the target time period, wherein the target network model is configured to predict a data amount of a next time period based on data amounts of a previous time period and a current time period; and determining a number of target regions based on the third data amount within the target time period, and partitioning, based on the number of target regions, a space in the database table configured to store the data to be stored.

Abstract: A driving circuit for driving a piezoelectric load, can include: a rechargeable power supply; a power stage circuit coupled between the rechargeable power supply and the piezoelectric load; where during a first operation interval of an operation period, the rechargeable power supply charges the piezoelectric load through the power stage circuit, such that a power supply voltage signal provided to the piezoelectric load in the first operation interval corresponds to a reference voltage in a first interval; and where during a second operation interval of the operation period, the piezoelectric load charges the rechargeable power supply through the power stage circuit, such that the power supply voltage signal in the second operation interval corresponds to the reference voltage in a second interval.

Abstract: A driving circuit and a driving method are provided. The driving circuit includes a charging circuit and a discharging circuit. The charging circuit is configured to receive an input voltage to charge the piezoelectric load. The piezoelectric load discharges electricity through the discharging circuit. Operation states of the charging circuit and the discharging circuit are controlled. During a first operation interval of an operation period, the charging circuit charges the piezoelectric load so that a power supply voltage signal provided to the piezoelectric load corresponds to the reference voltage in a first interval. During a second operation interval of the operation period, the piezoelectric load discharges electricity through the discharging circuit so that the power supply voltage signal corresponds to the reference voltage in a second interval. The driving circuit according to the present disclosure requires a few switches, thereby facilitating circuit integration.

Abstract: A driving circuit and a driving method are provided. The driving circuit includes an energy-storage capacitor, a charging circuit and a discharging circuit. The energy-storage capacitor is coupled between a piezoelectric load and the charging circuit. Operation states of the charging circuit and the discharging circuit are controlled, so that the charging circuit charges the energy-storage capacitor during a first operation interval of an operation period, to adjust a power supply voltage signal provided to the piezoelectric load to change with a reference voltage in a first interval, and at least the piezoelectric load discharges electricity through the discharging circuit during a second operation interval of the operation period, to adjust the power supply voltage signal to change with the reference voltage in a second interval. The driving circuit according to the present disclosure requires a few switches, thereby facilitating circuit integration.

Abstract: Systems, methods, and apparatuses are disclosed herein for directing, using an optical arrangement including one or more lenses, a main beam and a leading beam toward a specimen such that the main beam is incident on the specimen at a main beam incidence and the leading beam is incident on the specimen at a leading beam incidence. The main beam intensity is greater than a leading beam intensity of the leading beam. A TDI sensor receives electromagnetic radiation from the leading beam incidence, thereby generating a first accumulated charge portion, and receives electromagnetic radiation from the main beam incidence, thereby generating a second accumulated charge portion. A processor maps the first accumulated charge portion to a first FOV, thereby yielding leading beam data, and maps the second accumulated charge portion to a second FOV, thereby yielding main beam data.