Abstract: A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Abstract: A current fed high-frequency isolated matrix converter and the corresponding modulation and control schemes are provided. The converter includes a current source full-bridge converter, a high-frequency transformer, a matrix converter, and a three-phase filter. An optimized space vector modulation solution is used for controlling the converter, and by comparing magnitudes of three-phase filter capacitor voltages to determine an action sequence of space vectors, switch tubes are turned on at zero voltage. A current source full-bridge circuit adopts a commutation strategy of a secondary clamping, and by calculating a leakage inductive current commutation time, full-bridge switch tubes are turned off at zero current to achieve safe and reliable commutation, and having advantages of a low system loss, a high efficiency, and a high power density.

Abstract: An array substrate includes sub-pixels arranged in an array, scan lines, and data lines on a base substrate, with any one of the sub-pixels including a pixel electrode and a switch transistor; wherein the pixel electrode is connected to a drain electrode of the switch transistor, a gate electrode of the switch transistor is connected to one of the scan lines, a source electrode of the switch transistor is connected to one of the data lines; and an active layer of the switch transistor of the sub-pixel is located between the pixel electrode of the sub-pixel and the data line connected to the sub-pixel.

Abstract: A current fed high-frequency isolated matrix converter and the corresponding modulation and control schemes are provided. The converter includes a current source full-bridge converter, a high-frequency transformer, a matrix converter, and a three-phase filter. An optimized space vector modulation solution is used for controlling the converter, and by comparing magnitudes of three-phase filter capacitor voltages to determine an action sequence of space vectors, switch tubes are turned on at zero voltage. A current source full-bridge circuit adopts a commutation strategy of a secondary clamping, and by calculating a leakage inductive current commutation time, full-bridge switch tubes are turned off at zero current to achieve safe and reliable commutation, and having advantages of a low system loss, a high efficiency, and a high power density.

Abstract: A display substrate, display panel, and method of fabricating the display substrate. The display substrate includes: a first thin film transistor on a substrate; a second thin film transistor on the substrate and on the same side of the substrate as first thin film transistor; a light blocking structure between the substrate and an active region of first thin film transistor. The light blocking structure is configured to block at least a portion of light incident on the active region of first thin film transistor, such that a ratio of area of an illuminated portion of the active region of first thin film transistor to an area of the active region of first thin film transistor is less than a ratio of area of an illuminated portion of an active region of second thin film transistor to an area of the active region of second thin film transistor.

Abstract: A display substrate, display panel, and method of fabricating the display substrate. The display substrate includes: a first thin film transistor on a substrate; a second thin film transistor on the substrate and on the same side of the substrate as first thin film transistor; a light blocking structure between the substrate and an active region of first thin film transistor. The light blocking structure is configured to block at least a portion of light incident on the active region of first thin film transistor, such that a ratio of area of an illuminated portion of the active region of first thin film transistor to an area of the active region of first thin film transistor is less than a ratio of area of an illuminated portion of an active region of second thin film transistor to an area of the active region of second thin film transistor.

Abstract: A method for manufacturing a display substrate includes a step of forming a pattern of a barrier layer and a pattern of a first electrode. The step of forming the pattern of the barrier layer and the pattern of the first electrode includes: forming a barrier layer film and a first electrode film sequentially; and forming the pattern of the barrier layer and the pattern of the first electrode by a single patterning process.

Abstract: The present application discloses a method of fabricating a display substrate having an organic layer for reducing parasitic capacitance between electrodes in different layers. The method includes forming the organic layer on a base substrate; subjecting the organic layer to a surface treatment process to descum organic residues from a surface of the organic layer; and forming a passivation layer on a side of the organic layer distal to the base substrate subsequent to subjecting the organic layer to the surface treatment process.

Abstract: A thin film transistor and manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes a source electrode, a drain electrode and an active layer; the source electrode, the drain electrode and the active layer are disposed in a same layer, the source electrode and the drain electrode are separately joined to the active layer through their respective side faces, a material of the source electrode and the drain electrode is metal, and a material of the active layer is a metal oxide semiconductor in correspondence with material of the source electrode and the drain electrode. With the thin film transistor, procedures can be decreased, thereby reducing costs.

Abstract: The embodiment of the present application discloses an array substrate, a liquid crystal display panel, and a display device, with first common electrode compensation lines being arranged within pixel regions which correspond to pixels provided with a minimal transmittance, by which first common electrode compensation lines a common electrode is charged so as to ensure a constant voltage on the common electrode. Moreover, since the first common electrode compensation lines are configured to overlap neither first signal lines nor second signal lines, a repairmen of the first signal lines or the second signal lines will not be adversely affected in case that there is short-circuit or open-circuit thereon. Besides, since the common electrode compensation lines are arranged within pixel regions provided with the lowest transmittance, the influence onto overall transmittance of the display panel is minimized relatively.

Abstract: A preparation method of a conductive via hole structure, a preparation method of an array substrate and a preparation method of a display device, the preparation method of the array substrate includes: forming a first metal layer (01) including the first metal structure (01a), forming a non-metallic film including a first part corresponding to the first metal structure (01a) and an organic insulating film (40?) in sequence; patterning the organic insulating film (40?) to form a first organic insulating layer via hole (41) corresponding to the first part; then baking to form an organic insulating layer (40); and then, removing the first part of the non-metallic film to form a non-metallic layer and expose the part of the surface (011) of the first metal structure (01a). This method can avoid the metal structure from being seriously oxidized.

Abstract: The present application discloses a method of fabricating a display substrate having an organic layer for reducing parasitic capacitance between electrodes in different layers. The method includes forming the organic layer on a base substrate; subjecting the organic layer to a surface treatment process to descum organic residues from a surface of the organic layer; and forming a passivation layer on a side of the organic layer distal to the base substrate subsequent to subjecting the organic layer to the surface treatment process.

Abstract: This disclosure provides a transparent conductive thin film, a substrate, a touch screen and a manufacturing method thereof, and a display device. The transparent conductive thin film comprises a first metal oxide layer, a metal layer and a second metal oxide layer arranged in a stacking manner.

Abstract: The embodiments of the present invention provide an array substrate and a method for manufacturing the same. The method includes: forming an ITO film on a substrate; performing an annealing treatment on the substrate; forming a gate metal film on the ITO film; and processing the ITO film and the gate metal film to obtain a common electrode pattern and a gate pattern. In the embodiments of the present invention, after film formation of ITO, an annealing process is performed. Water vapor residue in the ITO film can thus be released, thereby avoiding bumps on the interface between the ITO and other layers, and improving the yield of ADS products.

Abstract: This disclosure provides a transparent conductive thin film, a substrate, a touch screen and a manufacturing method thereof, and a display device. The transparent conductive thin film comprises a first metal oxide layer, a metal layer and a second metal oxide layer arranged in a stacking manner.

Abstract: The embodiment of the present application discloses an array substrate, a liquid crystal display panel, and a display device, with first common electrode compensation lines being arranged within pixel regions which correspond to pixels provided with a minimal transmittance, by which first common electrode compensation lines a common electrode is charged so as to ensure a constant voltage on the common electrode. Moreover, since the first common electrode compensation lines are configured to overlap neither first signal lines nor second signal lines, a repairmen of the first signal lines or the second signal lines will not be adversely affected in case that there is short-circuit or open-circuit thereon. Besides, since the common electrode compensation lines are arranged within pixel regions provided with the lowest transmittance, the influence onto overall transmittance of the display panel is minimized relatively.

Abstract: A preparation method of a conductive via hole structure, a preparation method of an array substrate and a preparation method of a display device, the preparation method of the array substrate includes: forming a first metal layer (01) including the first metal structure (01a), forming a non-metallic film including a first part corresponding to the first metal structure (01a) and an organic insulating film (40?) in sequence; patterning the organic insulating film (40?) to form a first organic insulating layer via hole (41) corresponding to the first part; then baking to form an organic insulating layer (40); and then, removing the first part of the non-metallic film to form a non-metallic layer and expose the part of the surface (011) of the first metal structure (01a). This method can avoid the metal structure from being seriously oxidized.

Abstract: The invention relates to the field of display design, and discloses an array substrate, a manufacturing method thereof, a display panel and a display device. The array substrate comprises a base substrate, and a peripheral gate line, a gate insulation layer, a peripheral data line and a protection layer which are formed on the base substrate in turn, wherein surface height of the protection layer corresponding to position where the peripheral gate line is located is higher than that of the protection layer corresponding to position where the peripheral data line is located. As such, when in contact with a peripheral wiring area of the array substrate, a foreign material is first in contact with the protection layer corresponding to position where the peripheral gate line is located, thereby reducing probability of crushing or scratching the peripheral data line by the foreign material, improving the stability of product performance.

Abstract: A thin film transistor and manufacturing method thereof, an array substrate and a display device are disclosed. The thin film transistor includes a source electrode, a drain electrode and an active layer; the source electrode, the drain electrode and the active layer are disposed in a same layer, the source electrode and the drain electrode are separately joined to the active layer through their respective side faces, a material of the source electrode and the drain electrode is metal, and a material of the active layer is a metal oxide semiconductor in correspondence with material of the source electrode and the drain electrode. With the thin film transistor, procedures can be decreased, thereby reducing costs.

Abstract: The present invention relates to the field of display technology, and provides a display substrate, its manufacturing method, and a display device. The method comprises a step of forming a pattern of a barrier layer and a pattern of a first electrode. The step of forming the pattern of the barrier layer and the pattern of the first electrode comprises: forming a barrier layer film and a first electrode film sequentially; and forming the pattern of the barrier layer and the pattern of the first electrode by a single patterning process.