Abstract: This application relates to the field of memory technology, in particular to a method and a system for remapping a row address on a multichannel DIMM. The method is applied to a memory controller, comprising: receiving a first read/write access address and extracting a first channel row address from the first read/write access address; encrypting and mapping the first channel row address through a key-based mapping method to obtain a second channel row address that corresponds to the first channel row address within a predetermined address range; forming a second read/write access address based on the second channel row address and unextracted address information in the first read/write access address, and performing read/write access to the DIMM based on the second read/write access address. The present application can alleviate side channel attack without causing degradation of read/write performance.

Abstract: The present disclosure provides methods and systems for image enhancement. The methods may include obtaining an initial image. The methods may include obtaining a first image and a second image by performing speckle noise reduction and edge enhancement on the initial image, respectively. The methods may further include determining a target image by performing a fusion operation on the first image and the second image.

Abstract: The present disclosure discloses methods, systems, and computer readable mediums for ultrasonic imaging. The method may include determining a target imaging mode according to information related to one or more imaging demands. The method may further include obtaining a target imaging result by performing an imaging operation according to the target imaging mode, wherein the one or more imaging demands may at least include a demand related to an imaging quality and/or a frame rate, the target imaging mode may include a first target imaging mode and/or a second target imaging mode, the first target imaging mode may be configured to perform an optimized imaging for a local imaging region, and/or the second target imaging mode may be configured to utilize a hybrid wave with at least two transmission beam types and/or at least two transmission frequencies for imaging.

Abstract: A register structure in an integrated circuit includes a first register element to store a first copy of data, a second register element to store a second copy of the data, and storage cells to store copies of a parity value of the data. The register structure also includes parity computing circuitry, coupled to the first and second register elements, to generate respective parity values of the first and second copies of the data. The register structure further includes a selection circuit to select between the first and second copies of the data based on a comparison of the respective parity values of the first and second copies of the data to a majority value of the copies of the parity value stored in the storage cells.

Abstract: A method of controlling access between multiple master devices to a shared resource is disclosed. The method includes receiving a request to access the shared resource from a first master device, and determining availability of the shared resource. If the shared resource is available, a successful response is returned to the first master device to establish access by the first master device to the shared resource. If the shared resource is unavailable, a failed response is returned to the first master device. During the resource's unavailability, it is automatically monitored for when the shared resource becomes available. Once available, the first master device is automatically notified.

Abstract: A register structure in an integrated circuit includes a first register element to store a first copy of data, a second register element to store a second copy of the data, and storage cells to store copies of a parity value of the data. The register structure also includes parity computing circuitry, coupled to the first and second register elements, to generate respective parity values of the first and second copies of the data. The register structure further includes a selection circuit to select between the first and second copies of the data based on a comparison of the respective parity values of the first and second copies of the data to a majority value of the copies of the parity value stored in the storage cells.

Abstract: A method and apparatus of controlling the flow of data transmitted from a transmitter to a receiver is disclosed. In a first mode, the method involves calculating an available buffer capacity based on buffer output information sent by the receiver to the transmitter. Data is transmitted from the transmitter to the receiver at a rate based on the calculated available buffer capacity. Upon detecting a threshold condition, the method switches to a second mode. The second mode involves sending transmit data in formation to the receiver, and updating the buffer output information based on the transmit data information.