Patents by Inventor Zhixuan GUO
Zhixuan GUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11762489Abstract: An array substrate includes a base substrate; a common electrode layer including a plurality of common electrodes, arranged in an array, a part of which being also used as first touch electrodes and another part of which being also used as second touch electrodes; a first conductive layer including a plurality of electrode connecting lines, each row of first touch electrodes being coupled serially by at least one electrode connecting line; and a second conductive layer including a plurality of first touch signal lines and a plurality of second touch signal lines, each row of first touch electrodes being coupled to at least one first touch signal line which is configured to transmit a first touch signal; each second touch electrode or each column of second touch electrodes being coupled to at least one second touch signal line which is configured to transmit a second touch signal.Type: GrantFiled: December 13, 2019Date of Patent: September 19, 2023Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Zhixuan Guo, Fengguo Wang, Yezhou Fang, Xinguo Wu, Hong Liu, Shiyu Zhang, Lei Li
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Publication number: 20230118501Abstract: An array substrate includes a base substrate; a common electrode layer including a plurality of common electrodes, arranged in an array, a part of which being also used as first touch electrodes and another part of which being also used as second touch electrodes; a first conductive layer including a plurality of electrode connecting lines, each row of first touch electrodes being coupled serially by at least one electrode connecting line; and a second conductive layer including a plurality of first touch signal lines and a plurality of second touch signal lines, each row of first touch electrodes being coupled to at least one first touch signal line which is configured to transmit a first touch signal; each second touch electrode or each column of second touch electrodes being coupled to at least one second touch signal line which is configured to transmit a second touch signal.Type: ApplicationFiled: December 13, 2019Publication date: April 20, 2023Inventors: Zhixuan GUO, Fengguo WANG, Yezhou FANG, Xinguo WU, Hong LIU, Shiyu ZHANG, Lei LI
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Array substrate with light shielding metal portions and manufacturing method thereof, display device
Patent number: 11448929Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.Type: GrantFiled: May 16, 2019Date of Patent: September 20, 2022Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.Inventors: Lei Yao, Dawei Shi, Wentao Wang, Lu Yang, Haifeng Xu, Lei Yan, Jinfeng Wang, Jinjin Xue, Fang Yan, Xiaowen Si, Lin Hou, Zhixuan Guo, Yuanbo Li, Xiaofang Li -
Publication number: 20220252926Abstract: Embodiments of the present disclosure provide a display substrate and a display panel. The display substrate has a light-transmissive region and a light-shielding region, and the light-shielding region includes a main support region and a secondary support region. The display substrate includes a substrate, an alignment layer on the substrate, and a convex structure on the alignment layer. The convex structure is on a side of the alignment layer distal to the substrate and at least in the main support region, and a distance from a surface of the convex structure distal to the substrate to the substrate is greater than a distance from a surface of the alignment layer distal to the substrate to the substrate.Type: ApplicationFiled: January 21, 2021Publication date: August 11, 2022Inventors: Kai LI, Feng LI, Yezhou FANG, Xinguo WU, Lei YAO, Chenglong WANG, Zhixuan GUO, Lei YAN
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Patent number: 11362115Abstract: The present disclosure relates to the technical field of display. Disclosed are an array substrate and a preparation method therefor, and a display panel and a display device. The array substrate includes: a substrate; multiple gate lines, wherein the gate lines are located on the substrate, and extend along a first direction; multiple data lines, wherein the data lines are located on the substrate, and extend along a second direction, and the gate lines and the data lines intersect to define multiple pixel areas; and a touch-control electrode wiring wherein the touch-control electrode wiring has the same direction as that of the gate lines, and is arranged insulated from the gate lines on a different layer, and the orthographic projection of the touch-control electrode wiring on the substrate at least has an overlapping area with the orthographic projection of part of the gate lines on the substrate.Type: GrantFiled: March 22, 2019Date of Patent: June 14, 2022Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Zhixuan Guo, Fengguo Wang, Yezhou Fang, Feng Li, Xinguo Wu, Hong Liu, Zifeng Wang, Lei Li, Kai Li, Liang Tian, Jing Zhao, Zhengkui Wang, Bo Ma, Haiqin Liang, Peng Liu
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Patent number: 11347334Abstract: An array substrate, a method for fabricating the same, and a display device are provided. The array substrate includes: a base substrate; touch electrode wiring including a first conductive layer and a second conductive layer, where the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer includes at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer; a planarization layer on the second conductive layer, where the planarization layer includes at least one first touch electrode contact hole; and touch electrode on the planarization layer, where the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.Type: GrantFiled: December 4, 2018Date of Patent: May 31, 2022Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Cenhong Duan, Dawei Shi, Fengguo Wang, Feng Li, Hong Liu, Xinguo Wu, Lu Yang, Wentao Wang, Zifeng Wang, Bo Ma, Yuanbo Li, Zhixuan Guo, Jing Zhao, Haiqin Liang
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Patent number: 11342460Abstract: A thin film transistor, a method for fabricating the same, an array substrate, a display panel, and a display device are provided. The thin film transistor includes a substrate, and an active layer on the substrate, wherein the active layer includes a poly-silicon layer and has a channel region and two electrode connection regions respectively on two sides of the channel region, and the channel region includes a plurality of lightly drain doping segments, which are spaced apart along from one of the electrode connection regions to the other electrode connection region, and channel segments located between the lightly drain doping segments.Type: GrantFiled: October 15, 2019Date of Patent: May 24, 2022Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Zhixuan Guo, Fengguo Wang, Yezhou Fang, Xinguo Wu, Hong Liu, Kai Li, Liang Tian, Shiyu Zhang
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Patent number: 11231800Abstract: A touch substrate includes a base, a plurality of touch electrodes arranged in an array on the base, and a plurality of signal lines disposed on a side of the plurality of touch electrodes proximate to or away from the base. The plurality of signal lines include a plurality of touch lines and a plurality of dummy touch lines. At least one of the plurality of touch electrodes is coupled to at least one of the plurality of touch lines. The at least one touch line is configured to transmit touch signals. The at least one touch electrode is coupled to at least one of the plurality of dummy touch lines.Type: GrantFiled: February 14, 2020Date of Patent: January 25, 2022Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xinguo Wu, Fengguo Wang, Zhixuan Guo, Hong Liu, Bo Ma, Yu Feng, Shicheng Song
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Patent number: 11222908Abstract: An array substrate is provided. The array substrate includes a base, a first electrode and a second electrode which are on the base and a touch line on the base, both the first electrode and the second electrode are configured to transmit a display signal, the touch line is configured to transmit a touch signal; the first electrode and the touch line are respectively in different layers, and an orthographic projection of the first electrode on the base at least partially overlaps with an orthographic projection of the touch line on the base. A preparation method of the array substrate and a touch display panel are further provided.Type: GrantFiled: August 6, 2018Date of Patent: January 11, 2022Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xinguo Wu, Fengguo Wang, Dawei Shi, Hong Liu, Zifeng Wang, Feng Li, Bo Ma, Zhixuan Guo, Yuanbo Li, Jing Zhao, Cenhong Duan, Haiqin Liang
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Patent number: 11195484Abstract: The present disclosure provides a display panel, a method of driving the display panel and a display device. Each signal input sub-circuitry of the display panel includes at least two transistors. A same control signal is applied to control signal lines corresponding to a same signal input sub-circuitry, different control signals are applied to control signal lines corresponding to different signal input sub-circuitries, and time periods within which the different control signals are at active levels are staggered from each other. A sum of width-to-length ratios of channels of the at least two transistors is equal to a first predetermined value, and an overlapping area of the gate electrode of each of the at least two transistors relative to an active layer of the transistor is smaller than a second predetermined value in a direction perpendicular to a base substrate of the display panel.Type: GrantFiled: April 16, 2020Date of Patent: December 7, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Lei Li, Jun Fan, Le Ta, Yusheng Liu, Yongqiang Zhang, Mei Li, Yafei Li, Peng Liu, Zhixuan Guo
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Publication number: 20210373689Abstract: An array substrate, a method for fabricating the same, and a display device are provided. The array substrate includes: a base substrate; touch electrode wiring including a first conductive layer and a second conductive layer, where the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer includes at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer; a planarization layer on the second conductive layer, where the planarization layer includes at least one first touch electrode contact hole; and touch electrode on the planarization layer, where the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.Type: ApplicationFiled: December 4, 2018Publication date: December 2, 2021Inventors: Cenhong DUAN, Dawei SHI, Fengguo WANG, Feng LI, Hong LIU, Xinguo WU, Lu YANG, Wentao WANG, Zifeng WANG, Bo MA, Yuanbo LI, Zhixuan GUO, Jing ZHAO, Haiqin LIANG
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Patent number: 11163204Abstract: An array substrate, a display panel including the same, and a display device are provided. The array substrate includes: a base substrate and a planarization layer on the base substrate. A first conductive layer is disposed on a side of the planarization layer away from the base substrate. A first passivation layer is disposed on a side of the first conductive layer and the side of the planarization layer not being covered by the first conductive layer, away from the base substrate, and provided with a plurality of stress release openings. An insulating layer is disposed in the stress release openings and on a side of the first passivation layer away from the planarization layer. A second conductive layer is disposed on a side of the insulating layer away from the planarization layer.Type: GrantFiled: March 6, 2020Date of Patent: November 2, 2021Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Hong Liu, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Kai Li, Bo Ma
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Publication number: 20210333608Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a plurality of gate lines on a side of the base substrate; a plurality of data lines on a side of the plurality of gate lines away from the base substrate and intersecting with the plurality of gate lines; and a plurality of light shielding metal portions between the base substrate and each of the plurality of gate lines; respective one of the gate lines includes a plurality of gate line sub-segments separated by the plurality of data lines, respectively, every two adjacent gate line sub-segments in the respective one of the gate lines correspond to one of the light shielding metal portions, and the every two adjacent gate line sub-segments are connected in series through the one of the light shielding metal portions.Type: ApplicationFiled: May 16, 2019Publication date: October 28, 2021Inventors: Lei YAO, Dawei SHI, Wentao WANG, Lu YANG, Haifeng XU, Lei YAN, Jinfeng WANG, Jinjin XUE, Fang YAN, Xiaowen SI, Lin HOU, Zhixuan GUO, Yuanbo LI, Xiaofang LI
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Publication number: 20210333968Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a display area and a peripheral circuit area. The array substrate further includes a plurality of touch electrodes located in the display area; a plurality of touch signal lines connecting the plurality of touch electrodes to the peripheral circuit area; a plurality of first conductor lines extending in a same direction as the plurality of touch signal lines; and a plurality of second conductor lines extending in a different direction from the plurality of touch signal lines.Type: ApplicationFiled: November 30, 2018Publication date: October 28, 2021Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xinguo WU, Fengguo WANG, Dawei SHI, Hong LIU, Zifeng WANG, Feng LI, Bo MA, Zhixuan GUO, Yuanbo LI, Cenhong DUAN, Jing ZHAO
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Patent number: 11127885Abstract: Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface.Type: GrantFiled: March 22, 2020Date of Patent: September 21, 2021Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Hong Liu, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Dong Zhang, Yue Yang, Yulin Cui
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Patent number: 11121226Abstract: The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor includes: an active layer located on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source penetrating through the first interlayer dielectric layer, and connected to the active layer; a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; and a drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.Type: GrantFiled: January 29, 2019Date of Patent: September 14, 2021Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Lei Yan, Feng Li, Yezhou Fang, Jun Fan, Lei Li, Yanyan Meng, Lei Yao, Jinjin Xue, Chenglong Wang, Jinfeng Wang, Lin Hou, Zhixuan Guo
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Publication number: 20210217894Abstract: A CMOS thin film transistor, a method for manufacturing the same, and an array substrate are provided. The method includes: forming a semiconductor layer including an N-type region and a P-type region on a substrate, the N-type region is divided into a first region, a second region, a third region, a fourth region and a fifth region, the P-type region is divided into a sixth region, a seventh region and an eighth region; performing first N-type ion doping on the first region and the fifth region; performing first P-type ion doping on the N-type region; performing second P-type ion doping on the N-type region and the P-type region; performing second N-type ion doping on the first region, the second region, the fourth region, the fifth region, the sixth region and the eighth region; and performing third P-type ion doping on the sixth region and the eighth region.Type: ApplicationFiled: December 25, 2019Publication date: July 15, 2021Inventors: Lei YAO, Yezhou FANG, Feng LI, Lei YAN, Jinjin XUE, Chenglong WANG, Yanyan MENG, Jinfeng WANG, Lin HOU, Zhixuan GUO, Yuanbo LI, Xiaofang LI
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Publication number: 20210166645Abstract: The present disclosure provides a display panel, a method of driving the display panel and a display device. Each signal input sub-circuitry of the display panel includes at least two transistors. A same control signal is applied to control signal lines corresponding to a same signal input sub-circuitry, different control signals are applied to control signal lines corresponding to different signal input sub-circuitries, and time periods within which the different control signals are at active levels are staggered from each other. A sum of width-to-length ratios of channels of the at least two transistors is equal to a first predetermined value, and an overlapping area of the gate electrode of each of the at least two transistors relative to an active layer of the transistor is smaller than a second predetermined value in a direction perpendicular to a base substrate of the display panel.Type: ApplicationFiled: April 16, 2020Publication date: June 3, 2021Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Lei LI, Jun FAN, Le TA, Yusheng LIU, Yongqiang ZHANG, Mei LI, Yafei LI, Peng LIU, Zhixuan GUO
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Publication number: 20210159364Abstract: Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface.Type: ApplicationFiled: March 22, 2020Publication date: May 27, 2021Inventors: Hong LIU, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Dong Zhang, Yue Yang, Yulin Cui
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Publication number: 20210157185Abstract: An array substrate, a display panel including the same, and a display device are provided. The array substrate includes: a base substrate and a planarization layer on the base substrate. A first conductive layer is disposed on a side of the planarization layer away from the base substrate. A first passivation layer is disposed on a side of the first conductive layer and the side of the planarization layer not being covered by the first conductive layer, away from the base substrate, and provided with a plurality of stress release openings. An insulating layer is disposed in the stress release openings and on a side of the first passivation layer away from the planarization layer. A second conductive layer is disposed on a side of the insulating layer away from the planarization layer.Type: ApplicationFiled: March 6, 2020Publication date: May 27, 2021Inventors: Hong LIU, Yezhou FANG, Fengguo WANG, Xinguo WU, Zhixuan GUO, Haidong WANG, Liang TIAN, Kai LI, Bo MA