Abstract: A method and apparatus for a microprocessor with a cache that has the advantages given by a victim cache without physically having a victim cache is disclosed. In one embodiment, a victim flag may be associated with each way in a set. At eviction time, the way whose victim flag is true may be evicted. However, the victim flag may be reset to false if a superceding request arrives for the cache line in that way. Another cache line in another way may then have its victim flag made true.

Abstract: A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performed by the use of a more efficient prefetching mechanism.

Abstract: A process for growing by chemical vapor deposition a heteroepitaxial single crystal diamond is disclosed. The process provides a substrate which enables the growth of single crystal diamond which is vapor coated on an iridium film. An intermediate process for producing a composite composition with diamond nuclei is also described. Further described are composite compositions of metal oxide, iridium and single crystal diamond films or diamond nuclei. Single crystal diamond is useful in a variety of electronics and acoustics fields.

Abstract: Computer systems having two processors of different clock frequencies and different levels of power consumption. An interface circuit can select one of the two processors to operate at a time to reduce power consumption without compromising the system performance.

Abstract: A predictor of consecutive useless accesses, wherein consecutive useless accesses to a logic unit are counted and a next useless access is predicted to be within a plurality of ranges. Each of the plurality of ranges has a corresponding confidence predictor to track and provide a confidence level of whether a next access to the logic unit will be useless.

Abstract: A processor having asymmetric secondary processing resources. One disclosed embodiment includes a first execution resource to perform a first function and a second execution resource that also performs the second function, although the second processing resource is asymmetric to the first resource in that it has a lower throughput than the first processing resource. Switching logic switches execution from the first processing resource to the second processing resource in a reduced power consumption mode.

Abstract: A computer system includes a first processor, a second processor, and interprocessor communication logic (ICL). The first processor operates at a higher frequency, includes a more advanced micro-architecture, and consumes more power than the second processor. When the computer system is plugged in, the first processor is selected as the primary system processor. When the computer system is powered by a battery, the second processor is selected as the primary system processor. The second processor and the ICL may be integrated together on the same semiconductor chip.

Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.

Abstract: A method and apparatus provide power control for a multiple giga-hertz frequency integrated circuit. The method and apparatus include multiple levels of clock gating control circuitry and a clock distribution network to generate a low-skew system clock signal, and generate a gated clock signal, from the system clock signal, and distribute the gated clock signal to a plurality of local logic circuits in the integrated circuit.

Abstract: Computer systems having two processors of different clock frequencies and different levels of power consumption. An interface circuit can select one of the two processors to operate at a time to reduce power consumption without compromising the system performance.

Abstract: Computer systems having two processors of different clock frequencies and different levels of power consumption. An interface circuit can select one of the two processors to operate at a time to reduce power consumption without compromising the system performance.

Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.