Patents by Inventor Zhongda Li
Zhongda Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948087Abstract: The present disclosure provides a drop impact prediction method and system for heavy equipment airdrop based on a neural network. The drop impact prediction method includes the following steps: S1: acquiring a plurality of sets of sample data by using a finite element model for drop simulation of heavy equipment airdrop; S2: determining structural parameters of a BP neural network, and pre-processing the structural parameters; S3: constructing a BP neural network model; and S4: predicting a drop impact situation of heavy equipment airdrop in an actual application process by using the trained BP neural network model.Type: GrantFiled: October 26, 2023Date of Patent: April 2, 2024Assignee: Huazhong University of Science and TechnologyInventors: Renfu Li, Zhaojun Xi, Zhongda Wu, Yichao Li, Zhenlin Mei
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Patent number: 10446695Abstract: A JFET having vertical and horizontal channel elements may be made from a semiconductor material such as silicon carbide using a first mask for multiple implantations to form a horizontal planar JFET region comprising a lower gate, a horizontal channel, and an upper gate, all above a drift region resting on a drain substrate region, such that the gates and horizontal channel are self-aligned with the same outer size and outer shape in plan view. A second mask may be used to create a vertical channel region abutting the horizontal channel region. The horizontal channel and vertical channel may each have multiple layers with varying doping concentrations. Angled implantations may use through the first mask to implant portions of the vertical channel regions. The window of the second mask may partially overlap the horizontal JFET region to insure abutment of the vertical and horizontal channel regions.Type: GrantFiled: April 7, 2017Date of Patent: October 15, 2019Assignee: United Silicone Carbide, Inc.Inventors: Anup Bhalla, Zhongda Li
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Patent number: 10367099Abstract: A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: GrantFiled: July 16, 2018Date of Patent: July 30, 2019Assignee: United Silicon Carbide, Inc.Inventors: Zhongda Li, Anup Bhalla
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Patent number: 10367098Abstract: A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: GrantFiled: April 6, 2018Date of Patent: July 30, 2019Assignee: United Silicon Carbide, Inc.Inventors: Zhongda Li, Anup Bhalla
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Publication number: 20180342626Abstract: A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: ApplicationFiled: July 16, 2018Publication date: November 29, 2018Inventors: Zhongda Li, Anup Bhalla
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Patent number: 10121907Abstract: A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.Type: GrantFiled: September 16, 2016Date of Patent: November 6, 2018Assignee: United Silicon Carbide, Inc.Inventors: Anup Bhalla, Zhongda Li
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Patent number: 10056500Abstract: A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: GrantFiled: September 15, 2016Date of Patent: August 21, 2018Assignee: United Silicon Carbide, Inc.Inventors: Zhongda Li, Anup Bhalla
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Patent number: 10050154Abstract: A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: GrantFiled: January 13, 2017Date of Patent: August 14, 2018Assignee: United Silicon Carbide, Inc.Inventors: Zhongda Li, Anup Bhalla
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Publication number: 20180226513Abstract: A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: ApplicationFiled: April 6, 2018Publication date: August 9, 2018Inventors: Zhongda Li, Anup Bhalla
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Publication number: 20170213917Abstract: A JFET having vertical and horizontal channel elements may be made from a semiconductor material such as silicon carbide using a first mask for multiple implantations to form a horizontal planar JFET region comprising a lower gate, a horizontal channel, and an upper gate, all above a drift region resting on a drain substrate region, such that the gates and horizontal channel are self-aligned with the same outer size and outer shape in plan view. A second mask may be used to create a vertical channel region abutting the horizontal channel region. The horizontal channel and vertical channel may each have multiple layers with varying doping concentrations. Angled implantations may use through the first mask to implant portions of the vertical channel regions. The window of the second mask may partially overlap the horizontal JFET region to insure abutment of the vertical and horizontal channel regions.Type: ApplicationFiled: April 7, 2017Publication date: July 27, 2017Inventors: Anup Bhalla, Zhongda Li
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Patent number: 9653618Abstract: A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.Type: GrantFiled: October 21, 2015Date of Patent: May 16, 2017Assignee: United Silicon Carbide, Inc.Inventors: Anup Bhalla, Zhongda Li
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Publication number: 20170133518Abstract: A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: ApplicationFiled: January 13, 2017Publication date: May 11, 2017Inventors: Zhongda Li, Anup Bhalla
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Publication number: 20170117392Abstract: A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.Type: ApplicationFiled: September 16, 2016Publication date: April 27, 2017Inventors: Anup Bhalla, Zhongda Li
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Publication number: 20170117418Abstract: A JFET is formed with vertical and horizontal elements made from a high band-gap semiconductor material such as silicon carbide via triple implantation of a substrate comprising an upper drift region and a lower drain region, the triple implantation forming a lower gate, a horizontal channel, and an upper gate, in a portion of the drift region. A source region may be formed through a portion of the top gate, and the top and bottom gates are connected. A vertical channel region is formed adjacent to the planar JFET region and extending through the top gate, horizontal channel, and bottom gate to connect to the drift, such that the lower gate modulates the vertical channel as well as the horizontal channel, and current from the sources flows first through the horizontal channel and then through the vertical channel into the drift.Type: ApplicationFiled: October 21, 2015Publication date: April 27, 2017Inventors: Anup Bhalla, Zhongda Li
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Publication number: 20170018657Abstract: A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: ApplicationFiled: July 14, 2015Publication date: January 19, 2017Inventors: Zhongda Li, Anup Bhalla
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Publication number: 20170018627Abstract: A vertical JFET made by a process using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A maskless self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.Type: ApplicationFiled: September 15, 2016Publication date: January 19, 2017Inventors: Zhongda Li, Anup Bhalla
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Patent number: 9148139Abstract: Disclosed inventions are directed to advanced high-voltage switches with improved performance characteristics, increased reliability, and better compatibility with conventional gate drivers. The inventions disclosed herein implement a hybrid switch, comprising a high-voltage normally-on SiC VJFET, controlled via a low-voltage Si MOSFET in a cascode (Baliga-pair) configuration. The SiC VJFET and Si MOSFET are integrated monolithically at a wafer level, with the Si MOSFET fabricated on the Si layer that is directly adjacent to a dielectric layer on top of the SiC VJFET. Methods of making and operating these switches are also provided.Type: GrantFiled: August 4, 2014Date of Patent: September 29, 2015Assignee: United Silicon Carbide, Inc.Inventors: Anup Bhalla, Zhongda Li
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Publication number: 20150200662Abstract: Disclosed inventions are directed to advanced high-voltage switches with improved performance characteristics, increased reliability, and better compatibility with conventional gate drivers. The inventions disclosed herein implement a hybrid switch, comprising a high-voltage normally-on SiC VJFET, controlled via a low-voltage Si MOSFET in a cascode (Baliga-pair) configuration. The SiC VJFET and Si MOSFET are integrated monolithically at a wafer level, with the Si MOSFET fabricated on the Si layer that is directly adjacent to a dielectric layer on top of the SiC VJFET. Methods of making and operating these switches are also provided.Type: ApplicationFiled: August 4, 2014Publication date: July 16, 2015Inventors: Anup Bhalla, Zhongda Li
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Patent number: 8188514Abstract: An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.Type: GrantFiled: August 12, 2009Date of Patent: May 29, 2012Assignees: Rensselaer Polytechnic Institute, Toyota Jidosha Kabushiki KaishaInventors: Masahiro Sugimoto, Tat-Sing Paul Chow, Zhongda Li, Tetsu Kachi, Tsutomu Uesugi
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Publication number: 20100038681Abstract: An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.Type: ApplicationFiled: August 12, 2009Publication date: February 18, 2010Inventors: Masahiro SUGIMOTO, Tat-Sing Paul Chow, Zhongda Li, Totsu Kachi, Tsutomu Uesugi