Patents by Inventor Zhongguang Xu
Zhongguang Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240176508Abstract: A system with a memory device and a processing device operatively coupled with the memory device, to perform operations including identifying a lifecycle state associated with a segment of the memory device, selecting, based on the lifecycle state, an erase policy for performing an erase operation with respect to the segment, and causing the erase operation to be performed with respect to the segment in accordance with the erase policy.Type: ApplicationFiled: November 28, 2023Publication date: May 30, 2024Inventors: Yu-Chung Lien, Zhongguang Xu, Ronit Roneel Prakash, Zhenming Zhou
-
Publication number: 20240176496Abstract: Methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. The portion of memory is erased in response to determining that the portion of memory is invalid. A request to move an additional portion of memory to a free pool from the garbage pool is received. A free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. The erased portion of memory is moved from the garbage pool to the free pool.Type: ApplicationFiled: November 20, 2023Publication date: May 30, 2024Inventors: Zhongguang XU, Ronit Roneel PRAKASH, Murong LANG, Ching-Huang LU, Zhenming ZHOU
-
Publication number: 20240170090Abstract: In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.Type: ApplicationFiled: October 23, 2023Publication date: May 23, 2024Inventors: Peng ZHANG, Lei LIN, Zhongguang XU, Li-Te CHANG, Zhengang CHEN, Murong LANG, Zhenming ZHOU
-
Publication number: 20240153570Abstract: A processing device, operatively coupled with a memory device, determines a number of program/erase cycles performed on a block of the memory device. The processing device determines that the number of program/erase cycles performed on the block satisfies a first threshold criterion, wherein the first threshold criterion corresponds to a frequency interval for performing a threshold voltage integrity scan on the block. The processing device performs a threshold voltage integrity scan on the block to determine an error count associated with a current threshold voltage of at least one select gate device of the block. Responsive to the error count associated with the current threshold voltage of the at least one select gate device satisfying a second threshold criterion, the processing device determines a rate of change associated with the current threshold voltage of the at least one select gate device.Type: ApplicationFiled: October 27, 2023Publication date: May 9, 2024Inventors: Zhongguang Xu, Murong Lang
-
Publication number: 20240152287Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller receives a request to program data into an individual portion of the set of memory components and determines whether the request comprises host data or non-user targeted space (NUTS) data. The controller conditionally defines a partition for the individual portion of the set of memory components based on whether the request comprises host data or the NUTS data. The controller associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level offset used to access a charge distribution of data stored in the individual portion of the set of memory components.Type: ApplicationFiled: October 25, 2023Publication date: May 9, 2024Inventor: Zhongguang XU
-
Publication number: 20240145010Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Murong Lang, Ugo Russo, Niccolo' Righetti
-
Publication number: 20240105240Abstract: A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Inventors: Murong Lang, Zhenming Zhou, Jian Huang, Zhongguang Xu, Jiangli Zhu
-
Patent number: 11929127Abstract: A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.Type: GrantFiled: August 31, 2021Date of Patent: March 12, 2024Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Murong Lang, Zhenming Zhou
-
Publication number: 20240071506Abstract: A memory device may include a memory and a controller. The controller may be configured to receive a read command associated with a block of the memory. The controller may be configured to determine a block type associated with the block. The controller may be configured to identify, based on the block type, one or more read voltage offsets for a read operation associated with the block. The controller may be configured to perform the read operation based on the one or more read voltage offsets.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Zhongguang XU, Murong LANG, Zhenming ZHOU, Ugo RUSSO, Niccolo' RIGHETTI, Nicola CIOCCHINI
-
Publication number: 20240061601Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a memory reliability value associated with an individual portion of the set of memory components and selects a partition closing time for the individual portion of the set of memory components based on the memory reliability value. The controller defines a partition of the individual portion of the set of memory components based on the partition closing time and associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.Type: ApplicationFiled: August 22, 2022Publication date: February 22, 2024Inventor: Zhongguang XU
-
Patent number: 11901014Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.Type: GrantFiled: May 9, 2022Date of Patent: February 13, 2024Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Murong Lang, Ugo Russo, Niccolo' Righetti
-
Patent number: 11881284Abstract: A first read operation is performed on a first set of memory cells addressable by a first wordline (WL), and a second read operation is performed on a second set of memory cells addressable by a second WL, wherein the first set of memory cells and the second set of memory cells are comprised by an open TU of memory cells. A first threshold voltage offset bin associated with the first WL is identified. A second threshold voltage offset bin associated with the second WL is identified. Respective threshold voltage offset bins for each WL of a plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on at least one of the first threshold voltage offset bin and the second threshold voltage offset bin. Respective default threshold voltages for each WL of the plurality of WLs are updated based on the threshold voltage offset bins.Type: GrantFiled: December 9, 2021Date of Patent: January 23, 2024Assignee: Micron Technology, Inc.Inventors: Murong Lang, Zhenming Zhou, Jian Huang, Zhongguang Xu, Jiangli Zhu
-
Publication number: 20240020025Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is received. In response to determining that the request is from a host, a first error recovery operation is performed, wherein the first error recovery operation is associated with a first plurality of demarcation voltages. In response to determining that the request is from a controller, a second error recovery operation is performed, wherein the second error recovery operation is associated with a second plurality of demarcation voltages, wherein the second plurality of demarcation voltages comprises a greater number of demarcation voltages than the first plurality of demarcation voltages.Type: ApplicationFiled: September 26, 2023Publication date: January 18, 2024Inventors: Zhongguang Xu, Jian Huang, Tingjun Xie, Murong Lang, Zhenming Zhou
-
Patent number: 11861178Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.Type: GrantFiled: August 31, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Jian Huang, Tingjun Xie, Murong Lang, Zhenming Zhou
-
Publication number: 20230420066Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising receiving, from a host system, an enhanced erase command referencing a block; performing a lookup to determine whether the block is marked in a grown bad block (GBB) data structure used to track blocks that have a defective select gate; and responsive to determining that the block is marked in the GBB data structure, discarding the enhanced erase command.Type: ApplicationFiled: September 6, 2023Publication date: December 28, 2023Inventors: Zhongguang Xu, Zhenlei Shen, Murong Lang
-
Patent number: 11854644Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.Type: GrantFiled: December 14, 2021Date of Patent: December 26, 2023Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Zhenlei Shen, Murong Lang
-
Publication number: 20230386578Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Zhongguang Xu, Tingjun Xie, Murong Lang
-
Publication number: 20230360704Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.Type: ApplicationFiled: May 9, 2022Publication date: November 9, 2023Inventors: Zhongguang Xu, Nicola Ciocchini, Zhenlei Shen, Charles See Yeung Kwong, Murong Lang, Ugo Russo, Niccolo' Righetti
-
Patent number: 11763914Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of a memory sub-system is determined, the operating characteristic corresponding to execution of a first sequence of operations of an error recovery process. A determination is made that the value satisfies a condition. In response to the value satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.Type: GrantFiled: December 21, 2021Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Murong Lang, Zhenming Zhou
-
Patent number: 11762589Abstract: A current operating characteristic value of a unit of the memory device is identified. An operating characteristic threshold value is identified from a set of operating characteristic thresholds, where the current operating characteristic value satisfies an operating characteristic threshold criterion that is based on the operating characteristic threshold value. A set of write-to-read (W2R) delay time thresholds that corresponds to the operating characteristic threshold value is identified from a plurality of sets of W2R delay time thresholds. Each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level. A W2R delay time threshold associated with a W2R delay time threshold criterion is identified from the set of W2R delay time thresholds, where the W2R threshold criterion is satisfied by a current W2R delay time of the memory sub-system. A read voltage level associated with the identified W2R delay time threshold is identified.Type: GrantFiled: August 6, 2021Date of Patent: September 19, 2023Assignee: Micron Technology, Inc.Inventors: Zhongguang Xu, Tingjun Xie, Murong Lang, Zhenming Zhou