Patents by Inventor Zhonghai Shi
Zhonghai Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10867994Abstract: A vertical structure may be used as a high density capacitance for an integrated circuit. These thin vertical structures can be configured to operate as an insulator in a metal-insulator-metal (MIM) capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.Type: GrantFiled: March 2, 2018Date of Patent: December 15, 2020Assignee: Cirrus Logic, Inc.Inventors: Zhonghai Shi, Marc L. Tarabbia
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Publication number: 20200006551Abstract: Embodiments described herein relate to a method of manufacture of an LDMOS transistor an LDMOS transistor, and an integrated circuit comprising an LDMOS transistor. The method of manufacture of the LDMOS device comprises implanting a Fluorine dopant in a drift region of the LDMOS device in order to improve alignment between the drift region of the LDMOS transistor and a thicker area of a single gate oxide layer grown on the drift region and a channel region of the LDMOS transistor.Type: ApplicationFiled: June 25, 2019Publication date: January 2, 2020Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: Zhonghai SHI, Scott WARRICK
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Patent number: 10068779Abstract: In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.Type: GrantFiled: August 11, 2017Date of Patent: September 4, 2018Assignee: Cirrus Logic, Inc.Inventors: Zhonghai Shi, Vince Deems, Hong Tian
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Publication number: 20180190648Abstract: A vertical structure may be used as a high density capacitance for an integrated circuit. These thin vertical structures can be configured to operate as an insulator in a metal-insulator-metal (MIM) capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.Type: ApplicationFiled: March 2, 2018Publication date: July 5, 2018Applicant: Cirrus Logic, Inc.Inventors: Zhonghai Shi, Marc L. Tarabbia
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Patent number: 9929147Abstract: A vertical structure may be manufactured in a substrate of an integrated circuit, and that vertical structure used to form a high density capacitance for the integrated circuit. These thin vertical structures can be configured to operate as an insulator in a capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.Type: GrantFiled: May 2, 2016Date of Patent: March 27, 2018Assignee: CIRRUS LOGIC, INC.Inventors: Zhonghai Shi, Marc L. Tarabbia
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Publication number: 20170338126Abstract: In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.Type: ApplicationFiled: August 11, 2017Publication date: November 23, 2017Applicant: Cirrus Logic, Inc.Inventors: Zhonghai SHI, Vince DEEMS, Hong TIAN
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Patent number: 9761461Abstract: In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.Type: GrantFiled: June 5, 2014Date of Patent: September 12, 2017Assignee: Cirrus Logic, Inc.Inventors: Zhonghai Shi, Vince Deems, Hong Tian
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Publication number: 20160329321Abstract: A vertical structure may be manufactured in a substrate of an integrated circuit, and that vertical structure used to form a high density capacitance for the integrated circuit. These thin vertical structures can be configured to operate as an insulator in a capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.Type: ApplicationFiled: May 2, 2016Publication date: November 10, 2016Inventors: Zhonghai Shi, Marc L. Tarabbia
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Publication number: 20150303246Abstract: In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.Type: ApplicationFiled: June 5, 2014Publication date: October 22, 2015Inventors: Zhonghai Shi, Vince Deems, Hong Tian
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Patent number: 8687417Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.Type: GrantFiled: October 5, 2007Date of Patent: April 1, 2014Inventors: Ruigang Li, Jingrong Zhou, David Donggang Wu, Zhonghai Shi, James F. Buller, Akif Sultan, Fred Hause, Donna Michael
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Publication number: 20140078819Abstract: Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicant: Texas Instruments IncorporatedInventors: Xiaowei Deng, Wah Kit Loh, Anand Seshardi, Zhonghai Shi
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Patent number: 8654562Abstract: Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.Type: GrantFiled: May 22, 2012Date of Patent: February 18, 2014Assignee: Texas Instruments IncorporatedInventors: Xiaowei Deng, Wah Kit Loh, Anand Seshadri, Zhonghai Shi
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Publication number: 20130182490Abstract: Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.Type: ApplicationFiled: May 22, 2012Publication date: July 18, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaowei Deng, Wah Kit Loh, Anand Seshadri, Zhonghai Shi
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Patent number: 8329519Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.Type: GrantFiled: November 28, 2011Date of Patent: December 11, 2012Assignee: GLOBALFOUNDRIES, Inc.Inventors: Zhonghai Shi, David Wu, Mark Michael, Donna Michael, legal representative
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Publication number: 20120070987Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.Type: ApplicationFiled: November 28, 2011Publication date: March 22, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Zhonghai SHI, David WU, Mark MICHAEL, Donna Michael
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Patent number: 8134208Abstract: Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.Type: GrantFiled: September 26, 2007Date of Patent: March 13, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Zhonghai Shi, David Wu, Mark Michael, Donna Michael, legal representative
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Patent number: 8026142Abstract: A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed.Type: GrantFiled: May 8, 2009Date of Patent: September 27, 2011Assignee: GLOBALFOUNDRIES Inc.Inventors: Zhonghai Shi, Jingrong Zhou
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Patent number: 8003466Abstract: A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.Type: GrantFiled: April 8, 2008Date of Patent: August 23, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Zhonghai Shi, David Wu, Jingrong Zhou, Ruigang Li
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Patent number: 7838345Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.Type: GrantFiled: May 2, 2006Date of Patent: November 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Zhonghai Shi, Bich-Yen Nguyen, Héctor Sánchez
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Publication number: 20100285650Abstract: A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed.Type: ApplicationFiled: May 8, 2009Publication date: November 11, 2010Applicant: GLOBALFOUNDRIES, Inc.Inventors: Zhonghai SHI, Jingrong ZHOU