Abstract: An optical emitter includes a vertical cavity surface emitting laser (VCSEL), an equalization circuit coupled to the VCSEL; and a current source coupled to the VCSEL and the equalization circuit. The equalization circuit is configured to divert a first current from the current source to the VCSEL at a first data frequency and divert a second current greater than the first current from the current source to the VCSEL at a second data frequency higher than the first data frequency.

Abstract: An optical or an optoelectronic device and methods are provided for data transmission across two interconnects. First, an electrical signal is obtained from an interconnect. Next, the electrical signal is modulated. Within the modulated electrical signal, an occurrence of a transition is determined, in which a change in a power of the electrical signal by more than a threshold amount. In response to the determination of the occurrence of the transition, coefficients indicative of respective amounts of compensation to resolve or mitigate nonlinearities associated with the transition are determined. According to the coefficients, a filter is applied in a vicinity of the transition to obtain a modified electrical signal. The modified electrical signal is converted into an optical signal and coupled to a fiber to transmit the optical signal to a destination at a second interconnect.

Abstract: An optical or an optoelectronic device and methods are provided for data transmission across two interconnects. First, an electrical signal is obtained from an interconnect. Next, the electrical signal is modulated. Within the modulated electrical signal, an occurrence of a transition is determined, in which a change in a power of the electrical signal by more than a threshold amount. In response to the determination of the occurrence of the transition, coefficients indicative of respective amounts of compensation to resolve or mitigate nonlinearities associated with the transition are determined. According to the coefficients, a filter is applied in a vicinity of the transition to obtain a modified electrical signal. The modified electrical signal is converted into an optical signal and coupled to a fiber to transmit the optical signal to a destination at a second interconnect.

Abstract: A push-pull circuit for an opto-electronic device includes: an output node; a pull-up circuit that, in operation, controls a falling edge rate of an input signal to the opto-electronic device while sharing charge with the output node; and a pull-down circuit that, in operation, controls a rising edge rate of the input signal to the opto-electronic device while sharing charge with the output node.

Abstract: A push-pull circuit for an opto-electronic device includes: an output node; a pull-up circuit that, in operation, controls a falling edge rate of an input signal to the opto-electronic device while sharing charge with the output node; and a pull-down circuit that, in operation, controls a rising edge rate of the input signal to the opto-electronic device while sharing charge with the output node.

Abstract: A device, including a first current supply configured to provide a bias current to a load and a main current supply having a source terminal coupled in parallel with the load and configured to reduce a current value to the load below the bias current, is provided. The device includes a termination resistor coupled in series with the source terminal of the main current supply and configured to receive current from the source terminal of the main current supply when the source terminal of the main current supply is activated. The device also includes an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at common mode voltage when current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor.

Abstract: A device, including a switch configured to couple a current source with an output terminal upon receipt of a data signal, is provided. The device also includes a first variable capacitor coupled in parallel to the current source at a common node on a source terminal of the switch, wherein the first variable capacitor comprises multiple capacitive elements coupled in parallel and configured to be activated by a programmable signal, and wherein the programmable signal is selected to increase a charge transfer rate from an output terminal coupled to a load, when the switch is turned on. A system and a serial interface including the above device are also provided.

Abstract: A device, including a first current supply configured to provide a bias current to a load and a main current supply having a source terminal coupled in parallel with the load and configured to reduce a current value to the load below the bias current, is provided. The device includes a termination resistor coupled in series with the source terminal of the main current supply and configured to receive current from the source terminal of the main current supply when the source terminal of the main current supply is activated. The device also includes an auxiliary current supply having a sink terminal coupled to the termination resistor at a common node, and configured to maintain the common node at common mode voltage when current flows from the source terminal of the main current supply to the sink terminal of the auxiliary current supply and through the termination resistor.

Abstract: A device, including a switch configured to couple a current source with an output terminal upon receipt of a data signal, is provided. The device also includes a first variable capacitor coupled in parallel to the current source at a common node on a source terminal of the switch, wherein the first variable capacitor comprises multiple capacitive elements coupled in parallel and configured to be activated by a programmable signal, and wherein the programmable signal is selected to increase a charge transfer rate from an output terminal coupled to a load, when the switch is turned on. A system and a serial interface including the above device are also provided.

Abstract: An example driver circuit includes a termination voltage circuit and a termination element coupled to the termination voltage circuit. The driver circuit also includes a current source switch coupled the termination element via a node. The driver circuit further includes a current source coupled to the current source switch. The current source switch and the termination voltage circuit are controlled via a control signal. The termination voltage circuit is to generate a termination voltage to match a node voltage of the node based on the control signal. The driver circuit further includes a load coupled to the termination element and the current source switch via the node. The driver circuit further includes a load voltage source coupled to the load. The node voltage is generated based on the load and the load voltage source.

Abstract: An example device in accordance with an aspect of the present disclosure includes at least one segment driver circuit having a first circuit and a second circuit, to receive input signals and provide output signals. A given segment driver circuit is to protect reliability and enable reconfigurability by selectively resetting coupling capacitors, and selectively cutting off the input signals from their respective segment driver circuit.

Abstract: An example device in accordance with an aspect of the present disclosure includes at least one segment driver circuit having a first circuit and a second circuit, to receive input signals and provide output signals. A given segment driver circuit is to protect reliability and enable reconfigurability by selectively resetting coupling capacitors, and selectively cutting off the input signals from their respective segment driver circuit.

Abstract: An example driver circuit includes a termination voltage circuit and a termination element coupled to the termination voltage circuit. The driver circuit also includes a current source switch coupled the termination element via a node. The driver circuit further includes a current source coupled to the current source switch. The current source switch and the termination voltage circuit are controlled via a control signal. The termination voltage circuit is to generate a termination voltage to match a node voltage of the node based on the control signal. The driver circuit further includes a load coupled to the termination element and the current source switch via the node. The driver circuit further includes a load voltage source coupled to the load. The node voltage is generated based on the load and the load voltage source.

Abstract: In one example, a device may include a first push-pull driver with a first impedance and a push-pull driver unit with a second push-pull driver having a second impedance. The push-pull driver unit may be in parallel with the first push-pull driver. The device may further include a pulse generating unit to activate the push-pull driver unit for a delay time following an edge transition in an input signal. In one example, the device may have an output impedance that is less than the first impedance when the push-pull driver unit is activated.

Abstract: Apparatuses and methods for a self-biased delay looked loop with delay linearization are provided. One example delay locked loop (DLL) circuit (100, 200) can include a digital-to-analog converter (DAC) (104, 204, 304) and a bias generator (108, 208) communicatively coupled to an output of the DAC (106, 206, 306). The bias generator (108, 208) is configured to provide a clock signal and a bias signal. A delay control circuit (DCC) (109, 209) is communicatively coupled to the bias generator (108, 208). The DCC (109, 209) is configured to provide a delayed clock signal based on the clock signal and the bias signal. A DAC bias circuit (122, 222, 422) is communicatively coupled to the DAC (106, 206, 306) and configured to provide a feedback signal to the DAC (104, 204, 304) based on the bias signal.

Abstract: Methods, systems, and computer-readable media are provided for operating a vertical-cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include sending a signal to a driver to decrease an optical power of a vertical cavity surface emitting laser transmitter, and sending a signal to the driver associated with increasing the optical power by a particular amount in response to determining that the optical power is insufficient for reception by a receiver.

Abstract: Methods, systems, and computer-readable media are provided for operating a vertical-cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include sending a signal to a driver to decrease an optical power of a vertical cavity surface emitting laser transmitter, and sending a signal to the driver associated with increasing the optical power by a particular amount in response to determining that the optical power is insufficient for reception by a receiver.

Abstract: Methods, systems, and devices are provided for operating a vertical-cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include determining an output voltage of a vertical-cavity surface-emitting laser driver, determining a relationship between the output voltage and a reference voltage, and adjusting an output current of the vertical-cavity surface-emitting laser driver based, at least in part, on the determined relationship.

Abstract: Methods, systems, and computer-readable mediah are provided for operating a vertical-cavity surface-emitting laser. Operating a vertical-cavity surface-emitting laser can include sending a signal to a driver to decrease an optical power of a vertical cavity surface emitting laser transmitter, and sending a signal to the driver associated with increasing the optical power by a particular amount in response to determining that the optical power is insufficient for reception by a receiver.

Abstract: Apparatuses and methods for a self-biased delay looked loop with delay linearization are provided. One example delay locked loop (DU) circuit (100, 200) can include a digital-to-analog converter (DAC) (104, 204, 304) and a bias generator (188, 208) communicatively coupled to an output of the DAC (106, 206, 306). The bias generator (108, 206) is configured to provide a clock signal and a bias signal. A delay control circuit (DCC) (109, 209) is communicatively coupled to the bias generator (108, 208). The DCC (109, 209) is configured to provide a delayed clock signal based on the clock signal and the bias signal. A DAC bias circuit (122, 222, 422) is communicatively coupled to the DAC (106, 206, 306) and configured to provide a feedback signal to the DAC (104, 204, 304) based on the bias signal.