Abstract: A system may have sensors that gather information on users. The users may have portable electronic devices such as wristwatches, cellular telephones, and computers. The sensors may include facial recognition image sensors, fingerprint sensors, voice sensors configured to identify users by voice, and other biometric sensors. Pressure sensors may be used to measure the weight of users to help identify the users and/or to determine their age. Using the sensors, user identities and user positions may be ascertained. The system may have equipment such as adjustable seats, climate control systems, media systems, and other components that can be customized based on the identities and user positions.

Abstract: Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

Abstract: Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

Abstract: A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data.

Abstract: A hybrid PLL is provided that includes an digital integral path and an analog proportional path.

Abstract: A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.

Abstract: A phase lock loop (PLL) circuit includes a selection mode device before a phase detector and time-to-digital converter (TDC). In a first mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the reference clock signal. In a second mode, the selection mode device outputs two signals having consecutive rising edges that are spaced apart in time by substantially one period of the feedback clock signal. In a third mode, the selection mode device outputs the reference and feedback clock signals. The phase detector and TDC are configured to generate a signal: indicating the reference clock frequency in the first mode; indicating of the feedback clock frequency in the second mode; and indicating a phase/frequency difference between the feedback and reference clocks in the third mode. These signals are used to control a VCO clock signal.

Abstract: A hybrid PLL is provided that includes an digital integral path and an analog proportional path.

Abstract: A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data.

Abstract: A display panel is provided by the present disclosure. The display panel includes a plurality of repeatedly arranged display units each having an array of sub-pixels displaying a plurality of colors. In the display panel, a plurality of sub-pixels b displaying a first color are arranged in a first spatial isotropic configuration in the display panel, and a plurality of sub-pixels d displaying a second color are arranged in a second spatial isotropic configuration in the display panel. At least one of the first color and the second color contributes most to display resolution among the plurality of colors.

Abstract: In certain aspects, a voltage regulator includes a pass transistor having a drain coupled to an input of the voltage regulator, a source coupled to an output of the voltage regulator, and a gate. The voltage regulator also includes an amplifier having a first input coupled to a reference voltage, a second input coupled to a feedback voltage, and an output, wherein the feedback voltage is approximately equal to or proportional to a voltage at the output of the voltage regulator. The voltage regulator further includes a voltage booster having an input coupled to the output of the amplifier and an output coupled to the gate of the pass transistor, wherein the voltage booster is configured to boost a voltage at the input of the voltage booster to generate a boosted voltage, and to output the boosted voltage at the output of the voltage booster.

Abstract: In certain aspects, a voltage regulator includes a pass transistor having a drain coupled to an input of the voltage regulator, a source coupled to an output of the voltage regulator, and a gate. The voltage regulator also includes an amplifier having a first input coupled to a reference voltage, a second input coupled to a feedback voltage, and an output, wherein the feedback voltage is approximately equal to or proportional to a voltage at the output of the voltage regulator. The voltage regulator further includes a voltage booster having an input coupled to the output of the amplifier and an output coupled to the gate of the pass transistor, wherein the voltage booster is configured to boost a voltage at the input of the voltage booster to generate a boosted voltage, and to output the boosted voltage at the output of the voltage booster.

Abstract: A method and device for handling radio link failure is disclosed. The method is as follows. A device at network side requests a terminal device to send an uplink signal according to a predefined first period, and detects first signal quality. if the device at the network side determines for continuous M1 times that the first signal quality is lower than a predefined first threshold, the device at the network side requests the terminal device to send the uplink signal according to a predefined second period, and detecting second signal quality, wherein M1 is a predefined first value. When determining according to the second signal quality that restoration of a radio link of the terminal device is failed, the device at the network side releases network resources corresponding to the radio link of the terminal device. The predefined second period is larger than the predefined first period.

Abstract: An integrated circuit (IC) chip includes an on-chip analog signal monitoring circuit for monitoring a set of analog signals generated by one or more mixed signal cores within the IC chip, converting the analog signals into digital signals, storing the digital signals in an on-chip memory, and providing the digital signals to a test equipment upon request. The analog signal monitoring signal includes an on-chip reference generator for generating precise voltages and/or currents, a switching network for routing a selected reference signal to an analog-to-digital converter (ADC) for calibration purpose and for routing a selected analog signal from one of the mixed signal cores to the ADC for digitizing purposes. The IC chip further includes an on-chip memory for storing the digitized analog signals for subsequent accessing by a test equipment for analysis. The IC chip includes a digital analog test point (ATP) for outputting the digitized analog signals.

Abstract: Various examples provide a method and a system for spectrum handover in cognitive radio (CR) systems. According to the method, after detecting a user of an authorized system appears at a current working frequency, the base station generates a spectrum handover command and sends the spectrum handover command via a channel identified by the CR DWNDI to instruct the UEs in the cell to perform spectrum handover according to the spectrum handover command.

Abstract: The present invention proposes a method processing in random access procedure, comprising the following steps: when a Preamble transmitted by a random access node is detected by a base station, the base station calculating TA according to the Preamble detected by itself and transmitting it to the random access node; the base station receiving random access detection information reported from a transparent relay station and selecting a service node for the random access node; the base station receiving an uplink signaling transmitted by the random access node after the random access node adjusted the uplink timing advance according to TA calculated by the base station, and notifying the random access node of the access condition through a contention resolution message according to the selected service node, and the random access node performing an access procedure based on the access condition.

Abstract: Various examples of the present disclosure describe a random access method and device in a CR system. The method includes: generating, by a base station device, a spectrum handover command, wherein the spectrum handover command comprises random access backoff time parameter information; and sending, by the base station device, the spectrum handover command to a user equipment in a cell to instruct the UE to initiate, during a spectrum handover procedure, a random access procedure using the random access backoff time parameter information. According to the various examples of the present disclosure, the random access backoff time parameter information is carried in the spectrum handover command, so that a random access conflict is suppressed during the spectrum handover procedure of the CR system. A large number of UEs that intensively perform random access on a target working frequency are pre-dispersed in time.

Abstract: Disclosed are a method and device for data exchanging, and relates to communication technology. The embodiments of the present application includes: pre-allocating virtual resource to user terminals, and activating the virtual resource in case of need, so user terminals can use the pre-allocated resource to exchange data with network side. When inactive, the virtual resource can allocated to other users. For small data, irregular service, pre-allocation of virtual resource and activating it in case of need, can improve efficiency of use of resource. Meanwhile, dividing users into groups and scheduling by groups can reduce control overhead.

Abstract: A combinatorial test device is configurable to contemporaneously test one or more sensors of output devices free from user intervention. A device under test such as a user device is placed in a test fixture of the combinatorial test device. Under the control and monitoring of a test controller testing takes place. The testing may be performed for quality assurance after assembly or repair, or to determine the reliability of the device such as by testing the device until a particular life cycle value is reached or a component in the device fails.

Abstract: A display panel is provided by the present disclosure. The display panel includes a plurality of repeatedly arranged display units each having an array of sub-pixels displaying a plurality of colors. In the display panel, a plurality of sub-pixels b displaying a first color are arranged in a first spatial isotropic configuration in the display panel, and a plurality of sub-pixels d displaying a second color are arranged in a second spatial isotropic configuration in the display panel. At least one of the first color and the second color contributes most to display resolution among the plurality of colors.