Patents by Inventor Zhuowen Sun
Zhuowen Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240047376Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: ApplicationFiled: September 21, 2023Publication date: February 8, 2024Inventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
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Patent number: 11810867Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: GrantFiled: August 23, 2022Date of Patent: November 7, 2023Assignee: Invensas LLCInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
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Publication number: 20230059375Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: ApplicationFiled: August 23, 2022Publication date: February 23, 2023Inventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
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Patent number: 11462483Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: GrantFiled: December 16, 2019Date of Patent: October 4, 2022Assignee: Invensas LLCInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
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Patent number: 10700002Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.Type: GrantFiled: June 20, 2019Date of Patent: June 30, 2020Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Zhuowen Sun
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Publication number: 20200118939Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Applicant: Invensas CorporationInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
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Patent number: 10559537Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: GrantFiled: September 10, 2018Date of Patent: February 11, 2020Assignee: Invensas CorporationInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
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Patent number: 10522457Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.Type: GrantFiled: January 3, 2019Date of Patent: December 31, 2019Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Charles G. Woychik, Arkalgud R. Sitaram, Hong Shen, Zhuowen Sun, Liang Wang, Guilian Gao
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Publication number: 20190304904Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Applicant: Invensas CorporationInventors: Cyprian Emeka Uzoh, Zhuowen Sun
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Patent number: 10354976Abstract: Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.Type: GrantFiled: December 28, 2016Date of Patent: July 16, 2019Assignee: Invensas CorporationInventors: Min Tao, Hoki Kim, Ashok S. Prabhu, Zhuowen Sun, Wael Zohni, Belgacem Haba
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Patent number: 10332833Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.Type: GrantFiled: July 20, 2018Date of Patent: June 25, 2019Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Zhuowen Sun
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Patent number: 10325877Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.Type: GrantFiled: April 23, 2018Date of Patent: June 18, 2019Assignee: Invensas CorporationInventors: Javier A. Delacruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
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Publication number: 20190157199Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.Type: ApplicationFiled: January 3, 2019Publication date: May 23, 2019Inventors: Cyprian Emeka UZOH, Charles G. WOYCHIK, Arkalgud R. SITARAM, Hong Shen, Zhuowen SUN, Liang WANG, Guilian GAO
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Publication number: 20190027444Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: ApplicationFiled: September 10, 2018Publication date: January 24, 2019Applicant: Invensas CorporationInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
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Patent number: 10177086Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.Type: GrantFiled: April 13, 2018Date of Patent: January 8, 2019Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Charles G. Woychik, Arkalgud R. Sitaram, Hong Shen, Zhuowen Sun, Liang Wang, Guilian Gao
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Publication number: 20180331030Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.Type: ApplicationFiled: July 20, 2018Publication date: November 15, 2018Applicant: Invensas CorporationInventors: Cyprian Emeka Uzoh, Zhuowen Sun
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Patent number: 10115678Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.Type: GrantFiled: November 6, 2017Date of Patent: October 30, 2018Assignee: Invensas CorporationInventors: Abiola Awujoola, Zhuowen Sun, Wael Zohni, Ashok S. Prabhu, Willmar Subido
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Patent number: 10103093Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.Type: GrantFiled: February 24, 2017Date of Patent: October 16, 2018Assignee: Invensas CorporationInventors: Zhuowen Sun, Cyprian Emeka Uzoh, Yong Chen
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Publication number: 20180240773Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.Type: ApplicationFiled: April 23, 2018Publication date: August 23, 2018Applicant: Invensas CorporationInventors: Javier A. Delacruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
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Publication number: 20180233447Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.Type: ApplicationFiled: April 13, 2018Publication date: August 16, 2018Applicant: Invensas CorporationInventors: Cyprian Emeka UZOH, Charles G. WOYCHIK, Arkalgud R. SITARAM, Hong SHEN, Zhuowen SUN, Liang WANG, Guilian GAO