Patents by Inventor Zigmund Ramirez Camacho

Zigmund Ramirez Camacho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8692377
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: an L-plated lead; a die conductively connected to the L-plated lead; and an encapsulant encapsulating the L-plated lead and the die.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: April 8, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Patent number: 8669649
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a lead overhang protruding from a lead non-horizontal side and a lead ridge protruding from the lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming an encapsulation over the integrated circuit, the lead, and the package paddle, the encapsulation under the lead overhang.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 11, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8664038
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle and a terminal adjacent to the package paddle; mounting a stack paddle over the package paddle with the stack paddle at a non-center offset with the package paddle; mounting a stack integrated circuit over the stack paddle; and encapsulating the stack integrated circuit and the stack paddle.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: March 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Publication number: 20140048919
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Emmanuel Espiritu
  • Patent number: 8652881
    Abstract: An integrated circuit package system includes: forming an anti-peel pad having both a concave ring and an external terminal with the concave ring, having a peripheral wall, surrounding the external terminal; connecting an integrated circuit with the anti-peel pad; and forming an encapsulation over the integrated circuit, the concave ring, and the external terminal with the encapsulation under the peripheral wall.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: February 18, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Henry Descalzo Bathan
  • Patent number: 8643157
    Abstract: An integrated circuit package system comprising: forming a paddle having a hole and an external interconnect; mounting an integrated circuit device having an active side to the paddle with the active side facing the paddle and the hole; connecting a first internal interconnect between the active side and the external interconnect through the hole; and encapsulating the integrated circuit device, the paddle, the first internal interconnect, and the external interconnect with the external interconnect partially exposed.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: February 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Zigmund Ramirez Camacho, Jairus Legaspi Pisigan
  • Patent number: 8643166
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom body, a lead top body, and a lead top conductive layer directly on the lead top body, the lead top conductive layer having a top protrusion and a top non-vertical portion, the lead bottom body having a horizontally contiguous structure; connecting an integrated circuit to the top protrusion; and forming an encapsulation covering the integrated circuit and exposing a top non-vertical upper side of the top non-vertical portion.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: February 4, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8633578
    Abstract: An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8633062
    Abstract: A method of manufacture of an integrated circuit package system includes: forming a paddle, an outer lead, and an inner lead between the paddle and the outer lead; forming a non-vertical paddle edge of the paddle and a non-vertical lead edge of the inner lead facing the non-vertical paddle edge; and encapsulating an integrated circuit die over the paddle.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Henry Descaizo Bathan, Zigmund Ramirez Camacho, Amel Trasporto
  • Patent number: 8629537
    Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8617933
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead overhang at an obtuse angle to a lead top side and having a lead ridge protruding from a lead non-horizontal side, the lead overhang having a lead overhang-undercut side at an acute angle to a lead overhang non-horizontal side; forming a lead conductive cap completely covering the lead overhang non-horizontal side and the lead top side; forming a package paddle adjacent the lead; mounting an integrated circuit over the package paddle; and forming an encapsulation over the integrated circuit, the package paddle, and the lead.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu, Dioscoro A. Merilo
  • Patent number: 8604596
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a hole, a lead extension, and an exterior pad under the lead extension with the hole abutting the lead extension; connecting an electrical interconnect between an integrated circuit and the lead extension; forming an encapsulation over the integrated circuit and surrounding the electrical interconnect and through the hole; and removing a bottom portion of the lead frame resulting in a stand-off lead from the lead extension with the exterior pad on the stand-off lead.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 10, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8592252
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: November 26, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Patent number: 8569872
    Abstract: An integrated circuit package system includes: providing a die-pad with a predefined slot and an integrated circuit attached to the die-pad; connecting the integrated circuit to the die-pad with a bond wire; encapsulating the integrated circuit and the bond wire with an encapsulation; and partitioning the die-pad with partial saw isolation grooves along a single axis, and into a side pad, and a die attach pad.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: October 29, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Henry Descalzo Bathan, Il Kwon Shim, Zigmund Ramirez Camacho, Philip Lyndon Cablao, Jose Alvin Caparas
  • Patent number: 8558369
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a post of multiple plating layers having a base end with an inward protrusion, a connect riser, and a top end opposite the base end; positioning an integrated circuit device having a perimeter end facing the connect riser and the inward protrusion; attaching a bond wire directly on the inward protrusion and the integrated circuit device; and applying an encapsulation over the integrated circuit device, the bond wire, the inward protrusion, and around the post, the encapsulation exposing a portion of the base end and the top end of the post.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: October 15, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Frederick Rodriguez Gahilig, Jairus Legaspi Pisigan
  • Patent number: 8536690
    Abstract: A method of manufacture of an integrated circuit packaging system includes: attaching a semiconductor die to a die pad of a leadframe; forming a cap layer on top of the semiconductor die for acting as a ground plane or a power plane; and connecting the semiconductor die to the cap layer through a cap bonding wire.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: September 17, 2013
    Assignee: STATS CHIPPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Henry Descalzo Bathan, Guruprasad Badakere Govindaiah
  • Patent number: 8513801
    Abstract: An integrated circuit package system includes: mounting a first integrated circuit over a carrier; mounting an interposer, having an opening, over the first integrated circuit and the carrier with the interposer having an overhang over the carrier; connecting an internal interconnect, through the opening, between the carrier and the interposer; and forming an encapsulation over the first integrated circuit, the internal interconnect, and the carrier.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: August 20, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • Patent number: 8508026
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a connection structure having a component pad, an outer pad, and an inner pad, the inner pad between the component pad and the outer pad; forming a support structure between the inner pad and the outer pad; mounting an integrated circuit device over the component pad; attaching an interconnect to the integrated circuit device and the outer pad, the interconnect above the inner pad and supported by the support structure; and applying an encapsulation over the connection structure, the interconnect, and the integrated circuit device.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 13, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Henry Descalzo Bathan
  • Patent number: 8502358
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base structure having an intermediate lead with an intermediate concave side and an intermediate convex side, a peripheral lead with a peripheral concave side and a peripheral convex side, and a paddle with a paddle concave side and a paddle convex side; applying an inner multi-layer finish directly on the intermediate concave side, the peripheral concave side, and the paddle concave side; applying an outer multi-layer finish directly on the intermediate convex side, the peripheral convex side, and the paddle convex side; mounting an integrated circuit device over the inner multi-layer finish; attaching an interconnect directly to the inner multi-layer finish on the peripheral concave side and directly to integrated circuit device; and applying an encapsulation over the integrated circuit device, the interconnect, and the base structure, with the outer multi-layer finish exposed from the encapsulation.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 6, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8502371
    Abstract: An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated circuit die with the lead extending from and beyond the edge.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: August 6, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Henry Descalzo Bathan