Abstract: Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

Abstract: An apparatus includes: a first memory controller that corresponds with a first type of non-volatile memory device; a second memory controller that corresponds to a second type of non-volatile memory device, wherein the second type of non-volatile memory device is different from the first type of non-volatile memory device; an physical layer (PHY) interface; and an interface controller coupled to the PHY interface for controlling signal transmission by the PHY interface; wherein the PHY interface is selectively configurable or is user-configured to allow the PHY interface to communicate with one or more memory devices belonging to the first type, the second type, or both.

Abstract: Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise receiving data pieces from a plurality of channels of a non-volatile storage device, assembling the data pieces into one or more error correction code (ECC) encoded codewords, and triggering an ECC engine to decode a codeword to generate decoded data to be returned to a host when the codeword is assembled. Each codeword may have data pieces retrieved from different channels. Thus, a data unit containing one or more ECC codewords may be spread into multiple channels of a non-volatile storage device and access latency may be improved by accessing multiple channels in parallel. An averaging effect may be achieved for an ECC codeword and ECC failures may be reduced. Fast NANDs implementing the techniques disclosed herein may achieve ultra-fast access and response time while maintaining a high throughput.

Abstract: A storage device includes: a controller; a storage medium coupled to the controller; and a data security bridge comprising a security module and a key management module; wherein the security module is configured to perform data encryption and/or data decryption; and wherein the key management module is configured to obtain a first security key stored in the storage device, obtain a second security key received by the storage device, and perform a user authentication based on the first security key and the second security key.

Abstract: A device includes a combining circuitry that receives an incoming signal, and one or more delayed signals from a delay circuitry. The combining circuitry combines the incoming signal and the one or more delayed signals to generate a combined signal. The device includes a comparing circuitry that receives the combined signal from the combining circuitry, and compares a pulse width of the combined signal to a threshold pulse width. When the pulse width of the combined signal is greater than or equal to the threshold pulse width, the comparing circuitry provides the combined signal to an amplifier circuit and provides a null signal to the delay circuitry. The amplifier circuit generates a pulse width modulated (PWM) signal based on the combined signal.

Abstract: A system including a write module to write pilot data at predetermined locations in a page of memory cells that are interspersed with user data in the page. The pilot data has a first predetermined pattern and provides an indication of a disturbance experienced by the user data due to noise and a read, write, or erase operation performed on the page. A read module reads data from the predetermined locations subsequent to writing the pilot data. A signal processing module compares the data read from the predetermined locations with the pilot data and estimates, based on the comparison of the data read from the predetermined locations in the page with the pilot data, and the first predetermined pattern of the pilot data, the disturbance experienced by the user data due to the noise and the read, write, or erase operation performed on the page.

Abstract: A system includes, in at least one aspect, a storage device including patterned media and a head; and a read channel configured to: receive a DC readback signal from the head, the DC readback signal including position error signal (PES) information associated with a position of the head with respect to the patterned media, and determine the position of the head with respect to the patterned media based on a result of summing the DC components of the PES information.

Abstract: In aspects of concurrent sound source localization of multiple speakers, audio signals from two or more microphones are upsampled, and then the upsampled audio signals are time-multiplexed to a plurality of beamformers. A first sound source received at the two or more microphones is localized at a first beamformer, and a second sound source received at the two or more microphones is localized at a second beamformer, where localizing the second sound source is constrained by the localization of the first sound source. The beamformers can filter the upsampled audio signals using beamformer coefficients from the localizations to produce beamformed audio signals.

Abstract: A read channel module including an input, a location module and a generation module. The input is configured to receive a read-back signal from a rotating storage medium. The location module is configured to determine a location to insert a first imitation defect within the read-back signal. The first imitation defect imitates a first defect. The generation module is configured to (i) selectively generate the first imitation defect, and (ii) insert the first imitation defect in the read-back signal at the determined location.

Abstract: Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.

Abstract: A device includes a combining circuitry that receives an incoming signal, and one or more delayed signals from a delay circuitry. The combining circuitry combines the incoming signal and the one or more delayed signals to generate a combined signal. The device includes a comparing circuitry that receives the combined signal from the combining circuitry, and compares a pulse width of the combined signal to a threshold pulse width. When the pulse width of the combined signal is greater than or equal to the threshold pulse width, the comparing circuitry provides the combined signal to an amplifier circuit and provides a null signal to the delay circuitry. The amplifier circuit generates a pulse width modulated (PWM) signal based on the combined signal.

Abstract: A system including a read module, a delay buffer, and a least mean square module. The read module is configured to read charge levels of memory cells of a nonvolatile memory and to generate read signals based on the charge levels of the memory cells of the nonvolatile memory. The delay buffer is configured to delay the read signals and to generate delayed read signals. The least mean square module is configured to generate mean values of the charge levels used to program the memory cells based on (i) differences between the read signals and the delayed read signals and (ii) a scaling factor. The scaling factor is based on variations in the charge levels due to cycling of the memory cells of the nonvolatile memory.

Abstract: Data storage apparatus includes a plurality of drive units, each of the drive units including a plurality of memory channels, and a plurality of storage medium controllers. Each storage medium controller addresses at least one of the memory channels. Each of the storage medium controllers is incapable of performing file system operations. An integrated storage controller connected to each of the drive units performs all file system operations of the data storage apparatus. The integrated storage controller includes a central processing unit, a host interface, and at least one storage medium interface for communicating with the plurality of storage medium controllers. A method for operating such data storage apparatus includes performing, in the integrated storage controller, error correction across all of the memory channels, as well as redundancy and wear-leveling. Each storage medium controller may perform error correction across all of the memory channels addressed by that controller.

Abstract: A system including an interference module and a programming module. The interference module is configured to generate interference values based on (i) a state to which a memory cell is to be programmed and (ii) states of one or more memory cells located near the memory cell. The interference values indicate effects of the states of the one or more memory cells on the state to which the memory cell is to be programmed. The programming module is configured to determine a programming value to program the memory cell to the state based on one or more of the interference values. The one or more of the interference values are selected based on (i) the state to which the memory cell is to be programmed, and (ii) the states of the one or more memory cells.

Abstract: Systems, methods, and other embodiments associated with a detector that processes signals read from a storage device are described. According to one embodiment, the detector includes a signal estimator configured to generate an estimate of a control signal by determining characteristics of the control signal from a read signal. The read signal includes the data signal and the control signal embedded together. The signal estimator is configured to generate the estimate of the control signal as a function of the characteristics. The detector includes a cancellation unit configured to produce the data signal by cancelling the estimate of the control signal from the read signal.

Abstract: A system including a read module and a detector module. The read module is configured to generate a plurality of read signals by reading a plurality of memory cells located along a bit line or a word line. The detector module is configured to detect a sequence of data stored in the plurality of memory cells based on (i) the plurality of read signals, and (ii) a plurality of reference signals associated with the plurality of memory cells. One of the plurality of reference signals associated with a first memory cell of the plurality of memory cells includes one of a first signal and a second signal. The first signal is free of interference from a second memory cell adjacent to the first memory cell along the bit line or the word line. The second signal accounts for interference from the second memory cell.

Abstract: A control module for a memory system including a plurality of multi-bit memory cells. The control module includes a read module configured to receive, from a first storage region of a first memory cell of the plurality of multi-bit memory cells, a first signal, and generate a second signal based on the first signal. A signal detection module is configured to determine distances between the second signal and respective estimates of a plurality of noiseless signals associated with the first memory cell. The noiseless signals correspond to a combination of an ideal signal and an interference signal. The signal detection module is further configured to determine, from the estimates of the plurality of noiseless signals, a noiseless signal that matches most closely to the second signal. A data conversion module is configured to detect data stored in the first storage region based on the noiseless signal that matches most closely to the second signal.

Abstract: A defect emulator module for a rotating storage device includes a coefficient module that generates a first coefficient. A location module generates a location. A defect signal module selectively modifies a read-back signal based on the first coefficient and the location. The first coefficient includes an emulation of a first defect in the read-back signal.

Abstract: Adaptive memory read and write systems and methods are provided that may compute estimated means and variances of multi-level memory cells to facilitate writing and reading of data to and from the multi-level memory cells are described herein. The systems may include an apparatus comprising multi-level memory cells, and an estimation block configured to compute estimated means and variances of level distributions of the multi-level memory cells by processing signal samples provided by at least a subset of the multi-level memory cells, the estimated means and variances to be used to facilitate writing and/or reading of data to and/or from at least selected ones of the multi-level memory cells, the multi-level memory cells having M-levels where M is an integer greater than 1, and each of the level distributions is associated with a corresponding level of the M-levels.

Abstract: Reproduction of encoded data which includes a split-mark. FIR data corresponding to split-mark and FIR data affected by the split-mark due to inter-symbol-interference are identified. FIR data corresponding to the split-mark is removed from the received FIR data. Recovered data is created by removing incorrect inter-symbol-interference from the FIR data due to the split-mark, and adding correct inter-symbol-interference from codeword bits. The recovered data is stitched together with data unaffected by split-mark data.