Abstract: A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.

Abstract: Machine-readable media, methods, and apparatus are described to monitor and throttle issuance of transactions. In some embodiments, transactions are monitored during a monitoring window based upon cycle type. In response to determining that a threshold has been exceeded during the monitoring window, issuance of transactions during a throttling window are limited to a budget. Further, transactions issued during the throttling window consume a portion of the budget that based upon their cycle type.

Abstract: A memory controller is coupled to a memory device via a memory channel. The memory controller includes a command-per-clock detection unit that compares a portion of a current address with a portion of a previous address. If there is a match, then the memory controller can continue to assert a chip select line coupled to the memory device. The command-per-clock detection unit checks to see whether only certain low-order bits of the address lines are toggling between the current and previous addresses. Additional copies of address lines for particular low-order bits are provided to the memory device to reduce loading on the low order bit address lines, allowing the low order bit address lines to toggle quickly in order to avoid the necessity of inserting a one clock period wait state. If the command-per-clock detection unit does not find a match (meaning that more than the low order address bits are toggling) then the wait state is inserted by deasserting the chip select line for a clock period.

Abstract: A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.

Abstract: Embodiments of the present invention provide for adaptively tuning the memory idle timer value in real time. Selected memory idle clock cycles are sampled to dynamically determine an optimized memory idle timer value. To optimize latency during sampling, the number of page hits (NPH) and number of page misses (NPM) are multiplied by weighted values WPH and WPM, respectively, such that the weighted function (WPH*NPH)?(WPM*NPM) is maximized. The weight associated with a page miss (WPM) is greater than the weight associated with a page hit (WPH), resulting in a bigger penalty for a page miss than a page hit. The selected setting is continuously optimized.

Abstract: Machine-readable media, methods, and apparatus are described to monitor and throttle issuance of transactions. In some embodiments, transactions are monitored during a monitoring window based upon cycle type. In response to determining that a threshold has been exceeded during the monitoring window, issuance of transactions during a throttling window are limited to a budget. Further, transactions issued during the throttling window consume a portion of the budget that based upon their cycle type.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.

Abstract: A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.

Abstract: Embodiments of the present invention provide for adaptively tuning the memory idle timer value in real time. Selected memory idle clock cycles are sampled to dynamically determine an optimized memory idle timer value. To optimize latency during sampling, the number of page hits (NPH) and number of page misses (NPM) are multiplied by weighted values WPH and WPM, respectively, such that the weighted function (WPH * NPH)−(WPM * NPM) is maximized. The weight associated with a page miss (WPM) is greater than the weight associated with a page hit (WPH), resulting in a bigger penalty for a page miss than a page hit. The selected setting is continuously optimized.

Abstract: A method and apparatus for adjusting memory signal timings by shifting the timing of a clock signal generated by a memory controller relative to the time at which other signals begin to be transmitted by the memory controller.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.