Abstract: An array substrate, a testing method and a manufacturing method of the array substrate are disclosed. The array substrate comprises a first test line (3), a second test line (4), and first data lines (1) and second data lines (2) that are disposed alternately. The first data lines (1) are directly connected to the first test line (3), and the second data lines (2) are connected to the second test line (4) through switch elements (7); or, the second data lines (2) are directly connected to the second test line (4), and the first data lines (1) are connected to the first test line (3) through switch elements (7). With the array substrate, charges in the display region can be avoided from being transferred to a test line, thereby decreasing the accumulation of static electricity, and enhancing reliability of the short bar region.

Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

Abstract: The embodiments of the present disclosure provide an apparatus, system and method for testing electrical functions. The apparatus for testing electrical functions comprises: at least one clamping tool configured to be capable of being clamped in the vicinity of at least one bonding area of an electronic device; at least one row of probes configured to be electrically connected to multiple pins in the at least one bonding area respectively when the at least one clamping tool is clamped; and at least one multiplex switch. Each multiplex switch has a first terminal comprising multiple ports, and a second terminal comprising at least one port and capable of being connected to a measurement instrument, and the at least one multiplex switch is configured to turn on or turn off an electrical connection between the multiple ports of the first terminal and at least one port of the second terminal.

Abstract: An UV curing mask plate, comprising: a mask layer, wherein: the mask layer is arranged on the substrate, and has a position corresponding to alignment marks, selection marks and an area not covered by the sealing frame glue to be cured; the material of the mask layer is a material with the function of blocking UV light.

Abstract: The present invention provides a manufacturing method for a light barrier substrate which comprising steps of: forming a metal electrode pattern on a substrate through a first patterning process; forming an insulating layer above the substrate and the metal electrode pattern; forming a metal electrode via hole on the insulating layer and forming a channel pattern for a connecting line between a metal electrode and an exterior integrated circuit (IC) on the insulating layer, with a half tone make process, through a second patterning process; forming a transparent electrode layer pattern on the substrate on which the metal electrode via hole and the channel pattern are formed.

Abstract: An array substrate and manufacturing method thereof and display device are provided. The method of manufacturing the array substrate includes forming a pattern including a gate electrode, a gate line, a common electrode line and a gate insulating layer on a substrate; forming a pattern including a data line, a source electrode, a drain electrode and an active layer; forming a pattern including an insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer; forming a pattern including a first transparent electrode over the insulating interlayer; forming a pattern including a passivation layer over the first transparent electrode; and forming a pattern including a second transparent electrode over the passivation layer. The method can efficiently prevent the ITO process polluting the TFT channel.

Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

Abstract: The embodiments of the present disclosure provide an apparatus, system and method for testing electrical functions. The apparatus for testing electrical functions comprises: at least one clamping tool configured to be capable of being clamped in the vicinity of at least one bonding area of an electronic device; at least one row of probes configured to be electrically connected to multiple pins in the at least one bonding area respectively when the at least one clamping tool is clamped; and at least one multiplex switch. Each multiplex switch has a first terminal comprising multiple ports, and a second terminal comprising at least one port and capable of being connected to a measurement instrument, and the at least one multiplex switch is configured to turn on or turn off an electrical connection between the multiple ports of the first terminal and at least one port of the second terminal.

Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

Abstract: A discharge device and a display panel preparation system based thereon are disclosed. The discharge device includes a conductive contact terminal electrically connected with an electrostatic discharge contactor of a substrate to be processed; and a voltage controller electrically connected to the contact terminal for adjusting a voltage on the contact terminal. The discharge device is able to eliminate (e.g., neutralize) the static electricity on the substrate to be processed.

Abstract: The present invention discloses a method for manufacturing a thin-film transistor, comprising the steps of: forming a semiconductor active layer, and a doped semiconductor active layer; forming a source-drain metal layer; forming a channel region; and implanting ions for lowering the TFT leakage current into the surface of the semiconductor active layer in the channel region via ion implantation after forming the channel region. The invention further relates to a thin-film transistor, a TFT array substrate and a display device. The invention has the following beneficial effects: by implanting ions for lowering the TFT leakage current into the channel region, the electrical performance of a TFT may be improved, and the thickness of a semiconductor active layer in a channel region may be changed controllably.

Abstract: The invention discloses an array substrate, and a method for repairing a broken data line on an array substrate. The method for repairing a broken data line on an array substrate includes steps: performing a treatment on a part of a semiconductor layer corresponding to an opening in a data line so that the part of the semiconductor layer becomes a conductive region, and the ends of the opening in the data line are electrically connected to each other by the conductive semiconductor layer. The above method for repairing a broken data line provided by the invention is not affected by the linewidth of the data line so that the broken data line can be repaired in the case that the linewidth of the data line is relatively small.

Abstract: An embodiment of the present invention discloses a 3D barrier substrate and a method for manufacturing the same, and a display device in order to improve the utilization of facilities, increase the production efficiency, and decrease the cost of production. The method of manufacturing 3D barrier substrate comprises: forming a transparent electrode thin film on a substrate, and forming a passivation layer on the transparent electrode thin film; forming an transparent electrode and a passivation layer via hole by a patterning process, wherein the via hole is used for coupling the transparent electrode to the signal line; and forming a signal line, wherein the signal line is coupled to the transparent electrode through the via hole.

Abstract: The present invention provides a manufacturing method for a light barrier substrate which comprising steps of: forming a metal electrode pattern on a substrate through a first patterning process; forming an insulating layer above the substrate and the metal electrode pattern; forming a metal electrode via hole on the insulating layer and forming a channel pattern for a connecting line between a metal electrode and an exterior integrated circuit (IC) on the insulating layer, with a half tone make process, through a second patterning process; forming a transparent electrode layer pattern on the substrate on which the metal electrode via hole and the channel pattern are formed.

Abstract: A thin film transistor and manufacturing method thereof, an array substrate comprising the thin film transistor and manufacturing method thereof are provided. The method of manufacturing the thin film transistor comprises forming an active layer and a source-drain electrode layer, forming a photoresist layer on the source-drain electrode layer and forming a pattern of the photoresist layer by a pattern process; etching the source-drain electrode layer by using the pattern of the photoresist layer as a mask to form a pattern of the source-drain electrode layer including a source electrode and a drain electrode; and removing the photoresist, then etching the active layer by using the pattern of the source-drain electrode layer as a mask to form a pattern of the active layer.

Abstract: According to the method for manufacturing an array substrate of the present disclosure, when two non-adjacent conductive layers are electrically connected to each other through the via-holes, the insulating layers between the adjacent conductive layers may be etched by several etching processes so as to form the corresponding via-holes in the insulating layer, thereby to achieve the electrical connection between the non-adjacent conductive layers. Meanwhile, it is also able to achieve the electrical connection between the adjacent conductive layers through the via-holes in each etching process. In other words, when at least three conductive layers are electrically connected with each other through the via-holes, merely the insulating layer between the adjacent conductive layers is etched in each etching process.

Abstract: Provided is a manufacturing method of an array substrate with an etching stop layer. The method includes: forming a pattern including a gate, a gate line and a common electrode line on a substrate through a first patterning process; forming a gate insulation layer, an active layer film and an etching stop layer through a second patterning process; wherein, the etching stop layer corresponds to a gap between a source and a drain which are to be formed, and a via hole exposing the common electrode line is formed above the common electrode line; forming at least an active layer, a pattern including source, drain and data line and a protection layer through a third patterning process; wherein, the protection layer exposes a part of the drain; and forming at least a pixel electrode through a fourth patterning process; wherein, the pixel electrode is electrically connected with the drain.

Abstract: An array substrate and manufacturing method thereof and display device are provided. The method of manufacturing the array substrate includes forming a pattern including a gate electrode, a gate line, a common electrode line and a gate insulating layer on a substrate; forming a pattern including a data line, a source electrode, a drain electrode and an active layer; forming a pattern including an insulating interlayer over the pattern of the source electrode, the drain electrode and the active layer; forming a pattern including a first transparent electrode over the insulating interlayer; forming a pattern including a passivation layer over the first transparent electrode; and forming a pattern including a second transparent electrode over the passivation layer. The method can efficiently prevent the ITO process polluting the TFT channel.

Abstract: An array substrate including a base substrate is disclosed; the base substrate is divided into a pixel region and a peripheral circuit region, the pixel region sequentially includes a gate electrode, a gate insulation layer, a semiconductor active layer, a pixel electrode, a source/drain electrode, a passivation layer and a common electrode; the peripheral circuit region sequentially includes a first circuit line, the gate insulation layer, a second circuit line and the passivation layer. An orthogonal projection area of the second circuit line is at least partly overlapped with an orthogonal projection area of the first circuit line on the base substrate, and the second circuit line is directly electrically connected with the first circuit line through a via hole penetrating the gate insulation layer. A method for manufacturing the array substrate and a display device including the array substrate are also disclosed.

Abstract: An array substrate including a base substrate is disclosed; the base substrate is divided into a pixel region and a peripheral circuit region, the pixel region sequentially includes a gate electrode, a gate insulation layer, a semiconductor active layer, a pixel electrode, a source/drain electrode, a passivation layer and a common electrode; the peripheral circuit region sequentially includes a first circuit line, the gate insulation layer, a second circuit line and the passivation layer. An orthogonal projection area of the second circuit line is at least partly overlapped with an orthogonal projection area of the first circuit line on the base substrate, and the second circuit line is directly electrically connected with the first circuit line through a via hole penetrating the gate insulation layer. A method for manufacturing the array substrate and a display device including the array substrate are also disclosed.