Patents by Inventor Zu-Yi Wang

Zu-Yi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Latency error detection circuit for a measurement system
    Patent number: 5533037
    Abstract: A latency error detection circuit including two cascaded latches receiving a clock signal from a measuring system upon the occurrence of an event and correspondingly asserting a bit to a processing system, and a circuit for clearing the first latch after the processing system acknowledges detecting the bit being asserted. If the second latch is clocked before the first latch is cleared, the second latch sets an error bit indicating a latency error condition. The processor system monitors the error bit to determine whether a latency error has occurred.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: July 2, 1996
    Assignee: National Instruments Corporation
    Inventors: Jaffar Shah, Kosta Ilic, Joseph E. Peck, Zu-Yi Wang