Patents by Inventor Zuo Dai

Zuo Dai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230376670
    Abstract: A system and method updates a clock tree based on skew values of the circuit design. The clock tree is updated by obtaining a circuit design that includes circuit elements and a clock tree. The clock tree includes clock sources and clock sinks. Data path slack values for the clock tree are determined based on the clock sources and the clock sinks. Further, clock arrival values for the clock tree are determined based on the clock sources and the clock sinks. A first total local skew value of the circuit design is determined based on the data path slack values, and the clock arrival values, and updating the clock tree based on the first total local skew value.
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Inventors: Tao HUANG, Tao LIN, Min PAN, Zuo DAI, Jaehan JEON
  • Publication number: 20230334211
    Abstract: A system and method for changing a circuit design are described. The method includes generating a propagation graph for the circuit design and estimating slack values for some of the paths in the propagation graph. The method also includes making a virtual change to the circuit design and determining whether to accept or reject the change based on how the change affects the estimated slack values.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Inventors: Zuo DAI, Konstantinos TSIROGIANNIS, Tao HUANG, Jaehan JEON, Tobias BJERREGAARD, Tao LIN, Min PAN
  • Patent number: 10318684
    Abstract: Systems and techniques for clock tree optimization are described. An electronic design automation (EDA) tool can receive a graph that represents a circuit design, wherein a set of trees in the graph can correspond to a set of clock trees in the circuit design. For each tree in the set of trees, a set of leaf node pairs can be determined. Next, for each leaf node pair, a flow can be created in the graph between the two leaf nodes in the leaf node pair. Aggregate flows can be determined for edges in the graph based on the flows. A set of edges based on the aggregate flows can be identified, and then circuitry corresponding to the set of edges can be identified. Next, the identified circuitry in the circuit design can be optimized.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: June 11, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Zuo Dai, Aiqun Cao
  • Publication number: 20150269298
    Abstract: Systems and techniques for clock tree optimization are described. An electronic design automation (EDA) tool can receive a graph that represents a circuit design, wherein a set of trees in the graph can correspond to a set of clock trees in the circuit design. For each tree in the set of trees, a set of leaf node pairs can be determined. Next, for each leaf node pair, a flow can be created in the graph between the two leaf nodes in the leaf node pair. Aggregate flows can be determined for edges in the graph based on the flows. A set of edges based on the aggregate flows can be identified, and then circuitry corresponding to the set of edges can be identified. Next, the identified circuitry in the circuit design can be optimized.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 24, 2015
    Applicant: SYNOPSYS, INC.
    Inventors: Zuo Dai, Aiqun Cao
  • Patent number: 9009632
    Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 14, 2015
    Assignee: Synopsys, Inc.
    Inventors: Zuo Dai, Dick Liu, Ming Su
  • Patent number: 8843867
    Abstract: Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: September 23, 2014
    Assignee: Synopsys, Inc.
    Inventors: Scott Chase, Zuo Dai, Dick Liu, Ming Su
  • Publication number: 20140258953
    Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 11, 2014
    Applicant: SYNOPSYS, INC.
    Inventors: Zuo Dai, Dick Liu, Ming Su
  • Patent number: 8799835
    Abstract: Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: August 5, 2014
    Assignee: Synopsys, Inc.
    Inventors: Jon Bendicksen, Randy Bishop, Zuo Dai, John Hapli, Dick Liu, Ming Su
  • Publication number: 20140149955
    Abstract: Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.
    Type: Application
    Filed: January 29, 2014
    Publication date: May 29, 2014
    Applicant: SYNOPSYS, INC.
    Inventors: Scott Chase, Zuo Dai, Dick Liu, Ming Su
  • Patent number: 8719738
    Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 6, 2014
    Assignee: Synopsys, Inc.
    Inventors: Zuo Dai, Dick Liu, Ming Su
  • Patent number: 8713486
    Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: April 29, 2014
    Assignee: Synopsys, Inc.
    Inventors: Zuo Dai, Dick Liu, Ming Su
  • Patent number: 8677297
    Abstract: Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 18, 2014
    Assignee: Synopsys, Inc.
    Inventors: Scott I. Chase, Zuo Dai, Dick Liu, Ming Su
  • Patent number: 8661377
    Abstract: Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: February 25, 2014
    Assignee: Synopsys, Inc.
    Inventors: Jon Bendicksen, Randy Bishop, Zuo Dai, John Hapli, Dick Liu, Ming Su
  • Publication number: 20130298096
    Abstract: Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 7, 2013
    Inventors: Jon Bendicksen, Randy Bishop, Zuo Dai, John Hapli, Dick Liu, Ming Su
  • Publication number: 20130275938
    Abstract: Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.
    Type: Application
    Filed: May 16, 2013
    Publication date: October 17, 2013
    Inventors: Jon Bendicksen, Randy Bishop, Zuo Dai, John Hapli, Dick Liu, Ming Su
  • Publication number: 20130159949
    Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 20, 2013
    Applicant: SYNOPSYS, INC.
    Inventors: Zuo DAI, Dick LIU, Ming SU
  • Patent number: 8453103
    Abstract: Roughly described, while manually dragging shapes during IC layout editing, editing operations determine which edges of which shapes are moving at what speed ratios. Based on the edge information and the DRC rules, the system calculates and keeps track of the minimum of the maximum distance the edges are allowed to move with the cursor without violating DRC rules, in four linear directions and all corner directions. Once a next cursor destination point is known, a DRC clean destination point is calculated based on the linear and corner bounds. If the next cursor position is beyond a the push-through distance ahead of the new DRC clean point, the editing objects are moved to the user's destination point. Otherwise, the editing objects are moved to the new DRC clean destination point, thereby stopping movement at that point.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 28, 2013
    Assignee: Synopsys, Inc.
    Inventors: Jon Bendicksen, Randy Bishop, Zuo Dai, John Hapli, Dick Liu, Ming Su
  • Publication number: 20130132919
    Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.
    Type: Application
    Filed: December 19, 2012
    Publication date: May 23, 2013
    Applicant: SYNOPSYS, INC.
    Inventors: ZUO DAI, DICK LIU, MING SU
  • Patent number: 8448097
    Abstract: Roughly described, a design rule data set includes rules on derived layers. The rules are checked by traversing the corners of physical shapes, and for each corner, populating a layout topology database with values gleaned from that corner location, including values involving derived layers. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations, including violations of design rules defined on derived layers. Violations are reported in real time during manual editing of the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, scanning in the direction of the edge orientations. Scans stop only at corner positions on physical layers, and populate the layout topology database with what information can be gleaned based on the current scan line, including information about derived layers. The scans need not reach corners simultaneously.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: May 21, 2013
    Assignee: Synopsys, Inc.
    Inventors: Zuo Dai, Dick Liu, Ming Su
  • Publication number: 20130074024
    Abstract: Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.
    Type: Application
    Filed: November 13, 2012
    Publication date: March 21, 2013
    Inventors: Scott I. Chase, Zuo Dai, Dick Liu, Ming Su